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7/6/2012
7/6/2012
MAR PC IR
MDR R0 R1
. . .
Control
ALU
Rn-1
Processor
Computer Instructions
Assembly Language
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Example Instruction
MOVE NUM1,R1
Fetch
Execute
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Another Example
ADD #1,R1
Fetch
Execute
R1 1 + [R1]
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Single-Bus Structure
Input
Output
Memory
Processor
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ALU R
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MAR
1
6 6
MEM MDR
MUX
2 1 2 1
PC IR
2
6 MUX
REGS
A ALU R B
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PC
1
IR 2
A1 A2
1 2
REGS
MUX
ALU R
B NZVC
2 3
MDR 1
MAR
MEM
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System Software
Compiler
Assembler
Text Editor
Operating System
Handle I/O
Department of Information Technology 11
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Memory Performance
Main Memory
Cache Memory
Processor
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12
Processor Clock
CLK
Period (P)
R = 1/P
Rate (R)
1 GHz = 1/1ns
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13
Performance Equation
Processor Execution Time (T) Number of Machine Language Instructions (N) Average Steps per Machine Instruction (S) Clock Rate (R)
NS T R
Performance Measurement (Benchmarking)
Pipelining
I1 F1 E1 F2 I2 E2 F3 I3 E3
Sequential Execution I1 I2 I3 F1 E1 F2 E2 F3 E3
Pipelined Execution
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Parallel Processing
Parallel Execution
Superscalar
Shared-Memory Message-Passing
Multiprocessors
Multicomputers
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16
CISC vs RISC
Complex Instruction Set Computers (CISC)
Smaller N Larger S
Larger N Smaller S Easier to Pipeline
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17
Review
Binary Hex 2's-complement Overflow
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18