VHSICHDL

SOCRATES - IP CHANIA
July 2002
An Introduction to VHSIC Hardware Description Language by
Ing. Valerie Loosveld
Overview

What is VHDL, Applications, Benefits and Design Flow? VHDL language and syntax
General Structure of a .VHD file Signals & data types VHDL Operators Concurrent & Sequential Statements Synchronous logic & State machines Testbench & simulation
Exercises with VDHL

Designing with Modelsim
Socrates IP, July 2002
Overview

Exercises with VDHL

WHAT IS VHDL?

What is VHDL? Application area Benefits of using VHDL Limitations/drawbacks Abstraction levels Design flow & philosophy
What is VHDL
VHDL = double acronym

VHDL = VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit
Developed in the early 80s by the American Department of Defense Defined by international standards
IEEE Std 1076 1987 IEEE Std 1076 1993
Application area
Describe architecture and behavior of discrete electronic systems Modeling System Hardware Embedded systems: co-design & co-verification Hardware Implementation: CPLD, FPGA, ...
Benefits of Using VHDL
Design at higher level

very powerful language constructs locate problems in early stage
Device independent
use same code for different target devices choice of tools & vendors
Flexibility
IP re-use: libraries & components
Top-down philosophy
large projects with different teams of designers functional simulation of building blocks
Quick time-to-market and low cost

Limitations/drawbacks

Only digital system design The VHDL code may not always describe an optimal function Not always most effective use of resources
Abstraction levels
Behavioural
RTL
Logic
Layout
Abstraction levels (Contd)
Behaviour level:
functional description of the model no system clock simulatable, not synthesizable to create stimuli
RT (Register Transfer) level:

combinatorial logic and storage elements system clock simulatable and synthesizable
Logic level:
interconnect of logic gates and storage elements detailed timing
Layout:
detailed timing
10
Design flow
VHDL editor Behavioural
Device independent
optimisation RTL
Device fitting or Place & Route Software
Logic
Layout
Device dependent
11
Top-down design philosophy

Design entry
Allows:
early testing easy change of technology structured system design
no
Simulation
Results OK? yes Synthesis/optimisation no Results OK? yes
12
Timing analysis and layout

Overview

Exercises with VDHL

13
VHDL language and Syntax


General Structure of a .VHD file Signals & data types VHDL operators Concurrent & sequential statements Synchronous logic & state machines Testbench & simulation
General
Case insensitive
VHDL keyword: lower case letters self defined identifiers: upper case letters
Sequential statements
executed one after another functions, procedures
Concurrent statements
executed in parallel instantiation
15
General (Contd)
Signal types:
each signal has a type VHDL provides predefined types

bit
bit bit_vector integer . makes the code more readable useful in state machines
Process
Process Std_logic integer
user can define his own types

my _type
bit _vector (0 to 3) Process
Process
16
Overview

Exercises with VDHL

17
STRUCTURE OF A .VHD FILE


Entity & port modes Architecture & architecture bodies Process Package & package body Configuration Library
Entity

Describes the interface or black box No behavioral description

entity HALFADD is
SUM
port(A
: in std_logic;
: in std_logic;
SUM, CARRY : out std_logic
CARRY
); end HALFADD;
19
Port modes
IN:
read-only, no signal update
OUT:
write-only, signal update
entity EXAMPLE is port(A B : in std_logic; : out integer;
BUFFER:
read, signal update
C
D end EXAMPLE;
: inout bit;
: buffer std_logic);
INOUT:
bi-directional data flow
!!! PORT MODES HAVE TO MATCH

20
Architecture

Internal view of black box, description of the functionality of the entity must be associated with a specific entity one entity can have several architectures contains concurrent statements
architecture BEHAVE of HALFADD is
A +
SUM
-- declaration part begin
CARRY
-- definition part
SUM <= A xor B;

CARRY <= A and B; end BEHAVE;
21
Architecture bodies
Data flow description

specifies how data will be transferred from signal to signal concurrent (parallel) statements
Behavioural description
always process with an algorithm sequential statements
Structural description
connecting system with subsystems and components no description of behaviour
22
Data flow description
Example: tri-state buffer

Library IEEE; use ieee.std_logic_1164.all;
en d q
entity BUFFER is port(d, en : in std_logic;
: out std_logic);
end BUFFER;
architecture BUFFER_ARCH of BUFFER is begin q <= d when (en = 1) else Z; end BUFFER_ARCH;
23
Behavioural description
Example: tri-state buffer
Library IEEE; use ieee.std_logic_1164.all;
entity BUFFER is
port(d, en : in std_logic; q : out std_logic);
en d q
end BUFFER; architecture BUFFER_ARCH of BUFFER is
begin
process (en,d) begin if (en = 1) then q <= d; else q <= Z; end if; end process; end BUFFER_ARCH;
24
Structural description
Example: full adder

A
U1 N_SUM U2 N_CARRY2
SUM
CIN
N_CARRY1
CARRY
Contents of top-level full adder:

2 x component half adder from library signals to connect building blocks
25
Structural description (Contd)

Library IEEE; use ieee.std_logic_1164.all; use work.our_package.all;
Extra library added with component half adder
entity FULLADDER is
port(A, B, CIN SUM, CARRY end FULLADDER; architecture FULLADDER_ARCH of FULLADDER is : in std_logic; : out std_logic);
Entity description of top-level
signal N_SUM, N_CARRY1, N_CARRY2: std_logic;

component HALFADD port( A, B SUM, CARRY end component; begin U1: HALFADD port map ( A, B, N_SUM, N_CARRY1); U2: HALFADD port map (N_SUM, CIN, SUM, N_CARRY2); CARRY <= N_CARRY 1 OR N_CARRY2;
26
: in std_logic; : out std_logic);
Declaration of signals and used components
Component instantiation
end BUFFER_ARCH;
Process

Within an architecture Contains sequential statements Triggered by signals in sensitivity list Multiple processes interact concurrently
Parallel
Sequential
architecture .. of .. is begin process (a,b,c) begin -- sequential statements end process;
Parallel
Sequential
clock: process (d,e) begin -- sequential statements end process clock; end ..;
Process
Process
Parallel Parallel
Sequential Sequential
Process
Process
27
Package & package body
Collection of definitions:
component declarations constants user defined data types functions
package DEMO_PACK is -- constants -- data types -- components -- subprogram declarations
Possible to split a package into header and body section Items can be made visible to other design units by using the use clause Useful in teamwork
end DEMO_PACK;
package body DEMO_PACK is -- constant values
-- subprogram definitions end DEMO_PACK;
28
Package Example
Library ieee; use ieee.std_logic_1164.all;
package SMALL_PACKAGE is component BUFFER port(d, en : in std_logic; q : out std_logic);
Same component names and port list as in entity
end component; component DFF port(d, clk, rst, pst : in std_logic; q end component; end SMALL_PACKAGE; : out std_logic);
Compile this file together with the BUFFER and DFF VHDL files into library work.
29
Package Example (contd)

Library ieee; use ieee.std_logic_1164.all; use work.small_package.all; component DFF port(d, clk, rst, pst : in std_logic; q end component; entity DFF_EN is port(d, clk, rst, pst : in std_logic; q end DFF_EN; : out std_logic); begin U1 : DFF port map (d, clk, rst, pst, s); U2 : BUFFER port map (s, en, q); end DFF_EN_ARCH; : out std_logic);
architecture DFF_EN_ARCH of DFF_EN is signal s : std_logic; component BUFFER port(d, en : in std_logic; q : out std_logic);
end component;
Package declaration Structural description to instantiate components
30
Configuration
Like a part list

specifies which architecture will be used for each entity
configuration CFG_DFF_EN of DFF_EN is

for CFG_DFF_EN for U1 : DFF use entity work.DFF(RTL); end for;
Only object that can be simulated or synthesized Declared in architecture
for U2 : BUFFER use entity work.BUFFER(RTL); end for;
end for; end CFG_DFF_EN;
31
Library
Collection of compiled design units

entity, architecture, package, package body, configuration
Exists physically as a directory

Predefined libraries are ieee and work
32
Overview

Exercises with VDHL

33
SIGNALS & DATA TYPES


Signals and signal assignments Assignments with constant values
Standard data types

Standard logic Using standard logic
Arrays
Array assignments Enumerated types
Signals

Have a specific type Are declared

before the begin keyword of the architecture in port from the entity
Represent
mostly wires state of memory elements
N_SUM
U1
U2
SUM
N_CARRY2
CIN
N_CARRY1
CARRY
35
Signal Assignments

By means of Signal Assignment Statement <= Defines a Driver to that Signal
Same Concept as in Real Hardware
i.e. a logic gate driving an input
architecture BEHAVE of EXAMPLE is signal A, B : std_logic; begin B <= A;
-- Some other statements

end BEHAVE;
36
Assignments with constant values
Single signal : use single quotes

Load Q <= 1; <= Z;
Bus signals : use quotation marks

Value <= 101; Q <= 01--10;
37
Standard Data Types

Concept : Every type has a set of values it may take Type must be defined when signal is declared
They are located in the package STANDARD Always remember : types must match exactly
False True
Boolean
10 ns 25 ps 200 fs
Time
0 1
Bit
111 0000 010110

Bit_vector
a Z
9 A
VHDL Synthesis
String
256 0 -45
9.02
1.0 -37.4
Character
38
Integer
Real
Standard logic = recommended data types

Multi valued Logic defined in the package Std_Logic_1164 Very useful for simulation Values:

U X 0 1 Z W L H -
Uninitialized Unknown, strong drive Logic 0, strong drive Logic 1, strong drive High impedance Unknown, weak drive Logic 0, weak drive Logic 1, weak drive Dont care
Types:

std_ulogic, std_ulogic_vector = Unresolved std_logic, std_logic_vector = Resolved
39
Recommended use: std_logic, std_logic_vector

Using Standard Logic
Include Before Entity

Library name Package name
Library IEEE; use IEEE.std_logic_1164.all;
-- Makes library visible -- Makes all contents of the package visible
entity HALFADD is port ( A, B SUM, CARRY : in std_logic;
: out std_logic );
end HALFADD;
40
Bus signals

Group of Signals of the Same Type Define Size When Declaring Signal/Port Using to or downto Legal declarations:
signal signal A_BUS : B_BUS : std_logic_vector (4 downto 1); std_logic_vector (0 to 12);
Illegal declarations:
signal signal A_BUS : B_BUS : std_logic_vector (4 to 1); std_logic_vector (0 downto 12);
41
Bus signal assignments

Size of Array on Left & Right MUST be Equal Elements are Assigned by Position, NOT Element Number
Be Consistent in Defining the Direction of Your Arrays

signal signal A_BUS, B_BUS : C_BUS : std_logic_vector (3 downto 0); std_logic_vector (0 to 3);
B_BUS
<=
A_BUS;
B_BUS(3)
<=
A_BUS(0);
A_BUS
<=
C_BUS;
B_BUS (3) B_BUS (2) B_BUS (1) B_BUS (0)

42
A_BUS (3) A_BUS (2) A_BUS (1) A_BUS (0)
B_BUS (3) B_BUS (2) B_BUS (1) B_BUS (0)
C_BUS (0) C_BUS (1) C_BUS (2) C_BUS (3)
Bus Signal Assignment by Name

An Element of an Array can be Assigned by its Name A Range of the Array can be Assigned a Common Value
signal
A_BUS :
std_logic_vector (3 downto 0);
A_BUS
<=
(3 => 0, 1 downto 0 => 1, 2 => 0 );
43
Enumerated Types, user defined types
Type Declaration
Specifies a list of values that an object of that type can contain Only these values can be assigned to an object of a type, that are specified in its type definition.
is ( RESET, IDLE, RW_CYCLE, INT_CYCLE ) ;
Signal Assignment Rule
type MY_STATE
. . . signal signal . . . STATE STATE STATE . . .
44
STATE
MY_STATE; std_logic_vector (0 to 1);
TWO_BIT : <= <= <=
RESET ; 00 ; TWO_BIT;
Overview

Exercises with VDHL

45
VHDL operators

Logical Operators Relational Operators Arithmetic Operators Concatenation Slicing
Logical Operators

and, or, nand, nor, xor Equal Precedence not Higher Precedence Only Valid for Same Operand Types Round Brackets are used to Overcome Precedence Execute From Left to Right Across Statement Predefined (and overloaded) for: entity EXAMPLE is port ( A, B, C : in std_logic; Bit Z : out std_logic); Bit_vector end EXAMPLE; Boolean architecture X of EXAMPLE is std_ulogic, std_logic std_ulogic_vector, std_logic_vector begin <= A and not (B or C); Z
end X ;
47
Logical Operators on Bus Signals

Operands Same Length & Type Operations on Matching Elements

signal . . . A_BUS, B_BUS, C_BUS : std_logic_vector (3 downto 0);
Z_BUS
Z_BUS Z_BUS Z_BUS Z_BUS
<=
(3) (2) (1) (0)
A_BUS
<= <= <= <=
and B_BUS ; Equivalent to : A_BUS (3) and B_BUS (3) A_BUS (2) and B_BUS (2) A_BUS (1) and B_BUS (1) A_BUS (0) and B_BUS (0)
; ; ; ;
48
Relational Operators

> , < , >= , <= , = , /= Return a Boolean
Most often used with if-then-else statement Rules:

Operands must be of the same type Arrays can have different length
Align left Compare right
1 1
49
0 1
1 1
Arithmetic Operators

+ , - , * , / , ** , abs , mod , rem Pre-defined for

Integer Real (except mod and rem) Time

Bit_vector Std_ulogic_vector Std_logic_vector
Not Defined for

Operands must be Same Type
50
Vector Arithmetic

Requires Reference to Package of Functions Different Vendor = Different Package

library IEEE; Use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity ADD is port( A, B : in std_logic_vector (3 downto 0); Z : out std_logic_vector (3 downto 0) ); end ADD;
architecture RTL of begin Z <= A + B ; end RTL;
51
ADD
is
Concatenation

Uses Ampersand & Associating Single Bits & Vectors to Form Array
signal signal A, B, C, D : A_BUS, B_BUS : std_logic; std_logic_vector (3 downto 0);
signal
. . . A_BUS . . .
BYTE :
<=
&
&
&
D ;
BYTE
. . .
<=
A_BUS
&
B_BUS ;
52
Bus signal slicing

A Slice or Single Element of an Array can be Referenced The Direction of the Slice MUST match that of the Signal Declaration
signal signal
A_BUS, B_BUS : C_BUS :
std_logic_vector (0 to 3);
Legal Slicing
B_BUS (3 downto 2) <= 01 ;
Illegal Slicing
B_BUS (2 to 3) <= 01 ;
C_BUS (1 to 2) <= A_BUS (3 downto 2);
C_BUS (2 downto 1) <= A_BUS (2 to 3);
53
Overview

Exercises with VDHL

54
Concurrent & sequential statements

Difference Concurrent Statements
Boolean equations logical operators conditional signal assignment : when selective signal assignment : select process structure if then else structure case structure
Sequential Statements

For Loop
Difference
Concurrent Statements

Are executed outside a process Are executed at the same time Order independent = no priority
Sequential Statements

Are executed within a process Are executed one at a time Order dependent = priority
56
Conditional signal assignment : when

Only one target Must have an unconditional else
Conditions can overlap Priority encoding !!

entity BRANCH is port ( A, B, C, X, Y Z end BRANCH; : : in integer range 0 to 7; out integer range 0 to 7);
architecture USE_CONDITIONAL of begin Z <= A when X > 5 else B when Y < 7 else C; end USE_CONDITIONAL;
57
BRANCH
is
Selective signal assignment : select

Only one target, selection based on one signal No overlapping conditions
All choices must be specified

specifically or ; with others

entity BEANCH is port ( A, B, C, X : Z : end BRANCH; in integer range 0 to 7; out integer range 0 to 7);
architecture USE_SELECTED begin with X select Z <= B C A end USE_SELECTED;

58
of when when when
BRANCH
is
0 to 4, 5, others;
Process Structure

Executed when event on signal in sensitivity list Signals updated AT END of process Any signals can be in list A process can be running or suspended
Label
MUX: process begin if SEL = 1 Z else Z end if; end process MUX; <= B ; <= then (A, B, SEL )
Sensitivity List
A ;
59
if then- else structure

Condition is Boolean Expression Elsif Sequence if CONDITION

Executes 0 or 1 branches Conditions can overlap Priority encoder
then -- sequential statements end if ;
if
CONDITION then -- sequential statements else -- sequential statements end if ;
if
60
CONDITION then -- sequential statements elsif CONDITION then -- sequential statements elsif CONDITION then -- sequential statements else -- sequential statements end if ; Socrates IP, July 2002
if then- else example

library IEEE; use IEEE.std_logic_1164.all; entity IF_EXAMPLE is port( A, B, C, X : in std_logic_vector (3 downto 0); Z end IF_EXAMPLE; architecture begin process (A, B, C, X) A of IF_EXAMPLE is : out std_logic_vector (3 downto 0));
begin
if (X = 0000) Z elsif Z else Z <= C ; <= A ; then then
(X <= 0101) <= B ;
end if ;
61
end process ; end A;
case structure

No overlapping conditions All choices must be specified

specifically or ; with others
No priority encoding
case EXPRESSION is when VALUE_1 => -- sequential statements when VALUE_M to VALUE_N => -- sequential statements when others => -- sequential statements end case ;
62
case example
library IEEE; use IEEE.std_logic_1164.all; entity port CASE_EXAMPLE ( A, B, C, X : Z end CASE_EXAMPLE; architecture begin process begin case X is when when when end case ;
63
is in integer range 0 to 15; out integer range 0 to 15 );
of
CASE_EXAMPLE
is
(A, B, C, X)
0 Z 5 Z Z
to <= <= <=
=>
B ; => C ; => 0 ;
others
end process ; end A;
conc. & seq. statements : how to choose

When Select if-then-else case
Execution
concurrent
concurrent
sequential
sequential
Inside process ?
No
No
Yes
Yes
Selection based on
one or more signal
one signal
one or more signals
one signal
Targets
one
one
Not appropriate
Not appropriate
Overlapping
64
Yes
No
Yes
No
Conditions ?
For Loop

Iterate around a loop for a number of times Identifier

Must not be declared Integer type Local to the loop
Synthesis: Range must be fixed

for IDENTIFIER in RANGE -- statements end loop ; loop
65
For Loop Example

library IEEE; use IEEE.std_logic_1164.all; entity port( A EXAMPLE : in in is std_logic_vector (15 downto 0); integer range 0 to 15;
SEL : Z :
out std_logic );
end EXAMPLE; architecture begin process begin for I in 0 to 15 loop if SEL = I Z <= then (A, SEL) RTL of EXAMPLE is
A( I ) ;
end if; end loop; end process ;

66
end
RTL;
Overview

Exercises with VDHL

67
Synchronous logic & State machines

Clocked events

Synchronous / Asynchronous resets State machines in VHDL State machine example
Clocked events
Rising Clock Edge
process ( CLK ) begin if ( CLKevent and CLK = 1 ) then -- Default assignments -- Combinational logic end if; end process;
Falling Clock Edge

process ( CLK ) begin if ( CLKevent and CLK = 0 ) then -- Default assignments -- Combinational logic end if; end process;
Rule:
No other statements allowed outside the if structure No else clause
69
Resets
Asynchronous Reset
process ( CLK , RST ) begin if ( RST = 0 ) then -- Combinational logic elsif ( CLKevent and CLK = 1 ) then -- Default statements -- Combinational logic end if; end process;
Synchronous Reset
process ( CLK ) begin if ( CLKevent and CLK = 1 ) then if ( RST = 0 ) then -- Combinational logic else -- Default statements -- Combinational logic end if ; end if; end process;
Rules:
No other statements allowed outside the if structures No else clause after the edge detection
70
Finite state machines
FSM architecture
Combinational block of next state logic State registers Combinational output logic
Next State Logic State Registers Output Logic
Definitions
Enumerated type for the state vector definition State vector definition
71
FSM Example : CPU Controller Architecture

INT CYCLE
INT_REQ = '1' RESET
IDLE
RW = '1' DMA_REQ = '1'
RW CYCLE
DMA CYCLE
72
FSM Example : RTL Schematic

STATE
NEXT_STATE RW, INT_REQ, DMA_REQ
FSM Logic
State Registers
Output Logic
CLK
RESET
73
FSM Example : Definitions

Architecture RTL of FSM is type T_STATE is (IDLE, RW_CYCLE, INT_CYCLE, DMA_CYCLE ) ; signal STATE, NEXT_STATE : T_STATE -- Other definitions begin STATE_REG: process ( CLK, RESET ) begin -- Statements end process STATE_REG ;
FSM_LOGIC: process ( STATE, RW, INT_REQ, DMA_REQ) begin -- Statements end process FSM_LOGIC ;
OUTPUT_LOGIC: process ( STATE, RW, INT_REQ, DMA_REQ) begin -- Statements end process OUTPUT_LOGIC ; end RTL;
74
FSM Example : State Registers
STATE_REG: process ( CLK, RESET ) begin if ( RESET = 0 ) then STATE <= IDLE ; elsif ( CLKevent and CLK = 1 ) then STATE <= NEXT_STATE ; end if ; end process STATE_REG ;
75
FSM Example : FSM Logic

FSM_LOGIC: process ( STATE, RW, INT_REQ, DMA_REQ) begin NEXT_STATE <= STATE ; case STATE is when IDLE => if ( INT_REQ = 1 ) then NEXT_STATE <= INT_CYCLE ; elsif ( DMA_REQ = 1 ) then NEXT_STATE <= DMA_CYCLE ; elsif ( RW = 1 ) then NEXT_STATE <= RW_CYCLE ; end if ; when RW_CYCLE => -- Statements, e.g. trigger Read/Write FSM when INT_CYCLE => -- Statements, e.g. trigger Interrupt FSM when DMA_CYCLE => -- Statements, e.g. trigger DMA FSM end case ; end process FSM_LOGIC ;
76
FSM Example : Output Logic

Mealy FSM
OUTPUT_LOGIC: process ( STATE, RW, INT_REQ, DMA_REQ) begin Moore FSM -- Default output assignments case STATE is OUTPUT_LOGIC: process ( STATE ) when IDLE => begin -- Output assignments -- Default output assignments when RW_CYCLE => case STATE is -- Output assignments when IDLE => when INT_CYCLE => -- Output assignments -- Output assignments when RW_CYCLE => when DMA_CYCLE => -- Output assignments -- Output assignments when INT_CYCLE => end case ; -- Output assignments end process OUTPUT_LOGIC ; when DMA_CYCLE => -- Output assignments end case ; end process OUTPUT_LOGIC ;
77
Overview

Exercises with VDHL

78
Testbenches & simulation

Time in VHDL
wait statement after statement
VHDL for Stimuli

Process Stops Simple Signals Clock Signals
wait statement
wait for <specific time>;

Waits for a specific time and re-executes the process The process is re-invoked the line immediately below the wait statement
wait on <signal list>;

Waits on signal events of one or more of the in the list before re-executing
wait until <condition>;

The statement waits for an event on one of the signals in the condition. If the condition becomes true, the process re-executes the line immediately below the wait statement
wait;
wait suspends a process forever
Used to prevent infinite loops Useful in testbenches for applying stimuli only once
80
Wait Examples
STIMULUS: process begin SEL <= 0 ; BUS_B <= 0000 ; wait for 10 ns ; SEL <= 1 ; wait for 1 us ; -- other assignments end process STIMULUS;
STIMULUS: process begin SEL <= 0 ; BUS_B <= 0000 ; wait for 10 ns ; SEL <= 1 ; wait for 1 us ; -- other assignments wait ; end process STIMULUS;
81
Wait Examples (Contd)

Equivalent
process begin if ( A = 1 or B = 1 ) then Z <= 1 ; else Z <= 0 ; end if ; Suspends at wait wait on A, B ; end process ;
process ( A, B ) begin if ( A = 1 or B = 1 ) then Z <= 1 ; else Z <= 0 ; end if ; Suspends at bottom end process ;
Only for simulation
Preferred for Synthesis
82
Wait Examples (Contd)

Equivalent
process begin wait until ( CLKevent and CLK = 1 ) ; Q <= D ; end process ;
Suspends at wait
process ( CLK ) begin if ( CLKevent and CLK = 1 ) then Q <= D ; end if ; Suspends at bottom end process ;
Cannot model Asynchronous reset
Preferred for Synthesis
83
after Statement

Used to describe waveforms Used to describe delays
Not for Synthesis, only for modeling and simulation

-- Wave Form Description A <= 0, 1 after 5 ns, 0 after 10 ns ; wait for 5 ns ; B <= 1 ; -- Propagation delay -> used for modeling process ( CLK ) constant Tpd : time := 8 ns ; begin if ( CLKevent and CLK = 1 ) then Q <= D after Tpd; end if ; end process ; A <= B ; -- Equivalent A <= B after 0 ns ;
84
When does a Simulation Stop ?

If all processes are stopped Stopping processes with a sensitivity list

Stops if no more events occur on the signals in the sensitivity list Use a EndofSim boolean signal
Stopping processes without sensitivity list

Use wait; statement => wait forever Use a EndofSim boolean signal
85
Simple Signals
... constant step : time := 10 ns ; signal EndOfSim : boolean := false ; process begin a <= 0 ; b <= 1 ; rst <= 1 ; wait for step ; rst <= 0 ; wait for step ; a <= 1; wait for 3*step ; b <= 0 ; ... constant step : time := 10 ns ; signal EndOfSim : boolean := false ; process begin a <= 0, 1 after 2*step ; b <= 1, 0 after 5*step ; rst <= 1, 0 after step ;
-- To stop loops in other processes EndOfSim <= true after 5*step ;

wait ; end process ; ...
-- To stop loops in other processes EndOfSim <= true ;

wait ; end process ; ...
86
Equivalent
Clock Signals
... constant step : time := 10 ns ; signal EndOfSim : boolean := false ; clock: process begin if not EndOfSim then CLK <= '1'; wait for step; CLK <= '0'; wait for step; else wait; Clock process stops if EndOfSim = true end if; end process clock; Results in a Clock signal with period of 20 ns ...
87
Books on VHDL
A Guide to VHDL, Mazor & Langstraat, Kluwer Academic Publishers ISBN 0-7923-9387-2 A Designer's Guide to VHDL Synthesis Ott & Wilderotter Kluwer Academic Publishers ISBN 0-7923-9472-0
88

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SOCRATES - IP CHANIA

An Introduction to VHSIC Hardware Description Language by

Ing. Valerie Loosveld

Exercises with VDHL

Socrates IP, July 2002

Exercises with VDHL

Socrates IP, July 2002

VHDL = double acronym

Socrates IP, July 2002

Socrates IP, July 2002

Benefits of Using VHDL

Design at higher level

Quick time-to-market and low cost

Socrates IP, July 2002

Socrates IP, July 2002

Abstraction levels (Contd)

RT (Register Transfer) level:

Device fitting or Place & Route Software

Socrates IP, July 2002

Top-down design philosophy

Results OK? yes Synthesis/optimisation no Results OK? yes

Timing analysis and layout

Exercises with VDHL

Socrates IP, July 2002

VHDL language and Syntax

Socrates IP, July 2002

user can define his own types

bit _vector (0 to 3) Process

Socrates IP, July 2002

Exercises with VDHL

Socrates IP, July 2002

STRUCTURE OF A .VHD FILE

Describes the interface or black box No behavioral description

SUM, CARRY : out std_logic

Socrates IP, July 2002

entity EXAMPLE is port(A B : in std_logic; : out integer;

!!! PORT MODES HAVE TO MATCH

Socrates IP, July 2002

-- declaration part begin

SUM <= A xor B;

Socrates IP, July 2002

Data flow description

Socrates IP, July 2002

Data flow description

Example: tri-state buffer

entity BUFFER is port(d, en : in std_logic;

Socrates IP, July 2002

Example: tri-state buffer

Library IEEE; use ieee.std_logic_1164.all;

end BUFFER; architecture BUFFER_ARCH of BUFFER is

Socrates IP, July 2002

Example: full adder

Contents of top-level full adder:

Socrates IP, July 2002

Structural description (Contd)

Extra library added with component half adder

Entity description of top-level

signal N_SUM, N_CARRY1, N_CARRY2: std_logic;

: in std_logic; : out std_logic);

Declaration of signals and used components

Socrates IP, July 2002

architecture .. of .. is begin process (a,b,c) begin -- sequential statements end process;

Socrates IP, July 2002