Digital Integrated Circuits: A Design Perspective

Digital Integrated Circuits
2nd
Devices
Digital Integrated
Circuits
A Design Perspective
The Devices
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
July 30, 2002
2nd
Devices
Goal of this chapter
Present intuitive understanding of device
operation
Introduction of basic device equations
Introduction of models for manual
analysis
Introduction of models for SPICE
simulation
Analysis of secondary and deep-sub-
micron effects
Future trends

2nd
Devices
The Diode
n
p
p
n
B A
SiO
2
Al
A
B
Al
A
B
Cross-section of pn -junction in an IC process
One-dimensional
representation diode symbol
Mostly occurring as parasitic element in Digital ICs
2nd
Devices
Depletion Region
hole diffusion
electron diffusion
p n
hole drift
electron drift
Charge
Density
Distance
x +
-
Electrical
x
Field
x
Potential
V
W
2
-W
1
0
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostatic
potential.
2nd
Devices
Diode Current
2nd
Devices
Forward Bias
x
p
n0
n
p0
-W
1
W
2
0
p
n
(
W
2
)
n-region
p-region
L
p
diffusion
Typically avoided in Digital ICs
2nd
Devices
Reverse Bias
x
p
n0
n
p0
-W
1
W
2
0
n-region
p-region
diffusion
The Dominant Operation Mode
2nd
Devices
Models for Manual Analysis
V
D
I
D
= I
S
(e
V
D
/|
T
1)
+
V
D
+
V
Don
I
D
(a) Ideal diode model (b) First-order diode model
2nd
Devices
Junction Capacitance
2nd
Devices
Diffusion Capacitance
2nd
Devices
Secondary Effects
25.0 15.0 5.0 5.0
V
D
(V)
0.1
I
D

(
A
)

0.1
0
0
Avalanche Breakdown
2nd
Devices
Diode Model
I
D
R
S
C
D
+
-
V
D
2nd
Devices
SPICE Parameters
2nd
Devices
What is a Transistor?
V
GS
> V
T
R
on
S
D
A Switch!
|V
GS
|
An MOS Transistor
2nd
Devices
The MOS Transistor
Polysilicon
Aluminum
2nd
Devices
MOS Transistors -
Types and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS
Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with
Bulk Contact
2nd
Devices
Threshold Voltage: Concept
n+ n+
p-substrate
D S
G
B
V
GS
+
-
Depletion
Region
n-channel
2nd
Devices
The Threshold Voltage
2nd
Devices
The Body Effect
-2.5 -2 -1.5 -1 -0.5 0
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
V
BS
(V)
V
T

(
V
)
2nd
Devices
Current-Voltage Relations
A good ol transistor
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
DS
(V)
I
D

(
A
)

VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
V
DS
= V
GS
- V
T

2nd
Devices
Transistor in Linear
n
+
n
+
p-substrate
D
S
G
B
V
GS
x
L
V(x)
+
V
DS
I
D
MOS transistor and its bias conditions
2nd
Devices
Transistor in Saturation
n+ n+
S
G
V
GS
D
V
DS
> V
GS
- V
T
V
GS
- V
T
+
-
Pinch-off
2nd
Devices
Long-Channel Device
2nd
Devices
A model for manual analysis
2nd
Devices
The Deep-Submicron Era
Linear
Relationship
-4
V
DS
(V)
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
I
D

(
A
)

VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
2nd
Devices
Velocity Saturation
(V/m)

c
= 1.5
u

n

(

m

/
s
)

u
sat
= 10
5
Constant mobility (slope = )
Constant velocity
2nd
Devices
Perspective
I
D
Long-channel device
Short-channel device
V
DS
V
DSAT
V
GS
- V
T
V
GS
= V
DD
2nd
Devices
I
D
versus V
GS

0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
GS
(V)
I
D

(
A
)

0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
-4
V
GS
(V)
I
D

(
A
)

quadratic
quadratic
linear
Long Channel Short Channel
2nd
Devices
I
D
versus V
DS
-4
V
DS
(V)
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
I
D

(
A
)

VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
DS
(V)
I
D

(
A
)

VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
V
DS
= V
GS
- V
T

Long Channel Short Channel
2nd
Devices
A unified model
for manual analysis
S
D
G
B
2nd
Devices
Simple Model versus SPICE
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
-4
V
DS
(V)
I
D

(
A
)

Velocity
Saturated
Linear
Saturated
V
DSAT
=V
GT
V
DS
=V
DSAT
V
DS
=V
GT
2nd
Devices
A PMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0
-1
-0.8
-0.6
-0.4
-0.2
0
x 10
-4
V
DS
(V)
I
D

(
A
)

Assume all variables
negative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
2nd
Devices
Transistor Model
for Manual Analysis
2nd
Devices
The Transistor as a Switch
V
GS
> V
T
R
on
S
D
I
D
V
DS
V
GS
= V
DD
V
DD
/2 V
DD
R
0
R
mid
2nd
Devices
0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
7
x 10
5
V
DD
(V)
R
e
q

(
O
h
m
)
2nd
Devices
2nd
Devices
MOS Capacitances
Dynamic Behavior
2nd
Devices
Dynamic Behavior of MOS Transistor
D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB
2nd
Devices
The Gate Capacitance
t
ox
n
+
n
+
Cross section
L
Gate oxide
x
d
x
d
L
d
Polysilicon gate
Top view
Gate-bulk
overlap
Source
n
+
Drain
n
+
W
2nd
Devices
Gate Capacitance
S
D
G
C
GC
S
D
G
C
GC
S
D
G
C
GC
Cut-off
Most important regions in digital design: saturation and cut-off
2nd
Devices
Gate Capacitance
WLC
ox
WLC
ox
2
2WLC
o
x
3
C
GC
C
GCS
V
DS
/(V
GS
-V
T
)
C
GCD
0 1
C
GC
C
GCS
= C
GCD
C
GCB
WLC
ox
WLC
ox
2
V
GS
Capacitance as a function of VGS
(with VDS = 0)
Capacitance as a function of the
degree of saturation
2nd
Devices
Measuring the Gate Cap
2 1.52 1 2 0.5 0
3
4
5
6
7
8
9
10
3 10
2 16
2
V
GS
(V)
V
GS
G
a
t
e

C
a
p
a
c
i
t
a
n
c
e

(
F
)
0.5 1 1.5 2 2 2
I
2nd
Devices
Diffusion Capacitance
Bottom
Side wall
Side wall
Channel
Source
N
D
Channel-stop implant
N
A
1
Substrate N
A
W
x
j
L
S
2nd
Devices
Junction Capacitance
2nd
Devices
Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest
2nd
Devices
Capacitances in 0.25 m CMOS
process
2nd
Devices
The Sub-Micron MOS Transistor
Threshold Variations
Subthreshold Conduction
Parasitic Resistances
2nd
Devices
Threshold Variations
V
T
L
Long-channel threshold
Low V
DS
threshold
Threshold as a function of
the length (for low V
DS
)
Drain-induced barrier lowering
(for low L )
V
DS

V
T
2nd
Devices
Sub-Threshold Conduction
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D

(
A
)

V
T

Linear
Exponential
Quadratic
Typical values for S:
60 .. 100 mV/decade
The Slope Factor
ox
D
nkT
qV
D
C
C
n e I I
GS
+ =1 , ~
0
S is AV
GS
for I
D2
/I
D1
=10
2nd
Devices
Sub-Threshold I
D
vs V
GS

V
DS
from 0 to 0.5V
|
|
.
|
\
|
=

kT
qV
nkT
qV
D
DS GS
e e I I 1
0
2nd
Devices
Sub-Threshold I
D
vs V
DS

( )
DS
kT
qV
nkT
qV
D
V e e I I
DS GS
+
|
|
.
|
\
|
=

1 1
0
V
GS
from 0 to 0.3V
2nd
Devices
Summary of MOSFET Operating
Regions
Strong Inversion V
GS
>

V
T

Linear (Resistive) V
DS
<

V
DSAT

Saturated (Constant Current) V
DS
>

V
DSAT

Weak Inversion (Sub-Threshold) V
GS
s

V
T

Exponential in V
GS
with linear V
DS
dependence
2nd
Devices
Parasitic Resistances
W
L
D
Drain
Drain
contact
Polysilicon gate
D S
G
R
S
R
D
V
GS,eff
2nd
Devices
Latch-up

2nd
Devices
Future Perspectives
25 nm FINFET MOS transistor

Digital Integrated Circuits: A Design Perspective

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Integrated Circuits: A Design Perspective

Uploaded by

Copyright:

Available Formats

Digital Integrated Circuits

You might also like