ADC Power Scaling: Design Issues

Amit Tripathi
Faculty of Deptt. Of EN
NIET,Gr. Noida
Motivation for Power scaling
Increased portability
Demands low power design
Power scaling with sampling
frequency
ADCs that have a power which reduces
with sampling rate can significantly reduce
manufacturer and customer costs.
A single power scaleable ADC can be
used by a manufacturer to target multiple
applications with different performance
requirements saving development costs,
and reducing time to market.
(2 )( )
ENOB
s
Power
FOM
f
=
Digital Power
R
p
R
p
C
cycle DD
E QV =
E
P Ef
T
= =
2
VDD
P CV f =
Digital circuits only require power to
charge/discharge the load capacitance to the
final logic level. For a full cycle from zero to
one then back zero; Q = CV
DD
is transferred
f r o m V
D D
t o g r o u n d i n F i g . 1
Fig.1
Analog Power
P
analog
= IV
For analog power scaling we have to
made voltage and/or current as functions
of the sampling freque
i.e P(f
s
)=i(f
s
)V(f
s
)
supply voltage scaling
leads to move saturated device into triode region
reduced signal swing
significantly reduces ADC SNR
..Hence voltage scaling can only provide a minimal power-speed
dependency

Analog power
continue.
Bais current scaling
->opamp unity gain frequency is given by


C
load
R
out
g
m
Fig.2: Simplified small signal opamp model
m
ta
load
g
C
e =
1
2
at ox D
load
W
C I
C L
e =
Reduction of bias current with sampling
Frequency reduces the bandwidth of opamp
This may keep FOM constant.

According to square law equation
As transistor Drain current reduces
V
GS
->V
t

2
D
GS t
I
V V
W
k
L
= +
0
lim
D
I GS t
V V =
As V
GS
tends to V
t
channel region below the gate oxide become less inverted
And this drive the transistor in weak inversion region

Weak inversion operation of
transistor
Weak inversion operation is commonly used in
analog circuits that require very low power
consumption
g
m
/I
D
ratio is a maximum
A significant disadvantage of operation in the
weak inversion region however is the lack of
continuous, easy to manipulate models of
transistor operation in weak inversion.

Weak inversion model
A popular model (EKV),which describes transistor
operation in both strong and weak inversion regions. In
the EKV transistor model, drain source current is given
as the difference between a forward current, and a
reverse current.
I
DS
=I
F
-I
R

Where the forward current depends on gate and source
voltages, and the reverse current depends on gate and
drain voltages. For an NMOS transistor the current
components can be expressed as
( )
( )
2 2
( )
1
G TO S D
T
V V V
U
F R S
W
I I log e
L
k
| |
|
= +
|
\ .
Weak inversion model
continue
If the forward current is much larger than
the reverse current
----Transistor is saturated
If I
F
is comparable to I
R
----Transistor is in the ohmic or triode region
Weak inversion issues - mismatch
Transistor operation in weak inversion leads to increased
current mismatch
Stage
2
Stage
1
W/L W/L W/L
Stage
n
W/L
0.925uA 1.075uA 0.98uA
1uA
Stage
2
Stage
1
W/L W/L W/L
Stage
n
W/L
1uA 1.16uA 1.06uA
1.08uA
Bais power increased to
meet desired bandwidth
3 =15%
ID
Fig.3 Illustration of impact of mismatched current sources
Current scaling-Bias point
sensitivity
2 ( )
GS S
GS
dI
k V V
dV
~
g t s
T
V V V
nU
GS
dI
e
dV

~
In strong inversion
In weak inversion
if a transistor is acting as a current source to an opamp is in weak
inversion,a small variation of gate-source voltage on the transistor
due to (e.g.) noise coupling from a nearby digital circuit, thermal
fluctuations of a resistor acting as a reference current source, or
threshold mismatch, will cause the unity gain frequency of the opamp,
hence accuracy of the ADC to fluctuate significantly
Current scaling-IR Drop
2
m ox D
W
A g R R C I
L
~ =
Fig. 4: differential pair with RC load Fig. 5: differential pair with active load
For RC load
For active load
2
2
1
D
ox
m ds
D D
W
W
Cox I
C
L
L
A g r
I I

~ = =
current mirror transistors have a high sensitivity to bias
node fluctuations, thus it is possible that even a small IR
drop of a few mV between mirror transistor supply
voltages (due to e.g. physical separation on a larger chip)
could cause significant current mismatch hence
potentially reduced performance
M2
V
g1
V
g2
V
g2
V
g1
M1
M4
M3
Veff
3
=V
g1
-V
SS
-V
t
<Veff
1
Veff
4
=V
g2
-V
eff3
-V
t
<Veff
2
Veff
2
=Vg2-V
eff1
-V
t
Veff
1
=V
g1
-V
t
I
VSS
R
VSS
Fig. 6: impact of low currents on IR drops
Conclusion
This Paper discussed the dependency of power with
sampling rate for analog and digital systems. Current
scaling was shown as common technique to reduce
analog power with sampling rate.
It was shown that current scaling drives MOS
transistors deep into the weak inversion region for
extended reductions in sampling rate
Where due to less accurate models, circuit
design/fabrication could take several iterations to meet
desired performance.
Increased mismatch, bias point sensitivity, and IR drops
were also shown as limiting factors to the extent to which
current scaling can be used to reduce analog power