Ict123 W8

Centre for Computer Technology
ICT123 Computer Architecture

Week 08
Memory Systems
Content at a Glance

Review week7 Terminology Memory Hierarchy Principle of Locality Main memory - RAM, DRAM, SRAM, SDRAM, RDRAM Bulk Storage - HDDs, RAID, CDs Virtual Memory Cache
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
March 20, 2012
Simple address modes Simpler is better - easier design (and less time) Save space - simpler means smaller and faster Smaller means less heat Load/Store architecture Uniform instruction length Instruction pipelining
March 20, 2012
RISC
CISC

Richer instruction set, some simple, some very complex Instructions generally take more than 1 clock to execute Instructions of a variable size Instructions interface with memory in multiple mechanisms with complex addressing modes Microcode control No pipelining
(Yi gao, Shilang Tang, Zhongli Ding) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
March 20, 2012
CISC vs RISC (1)

For example: A=B+C CISC: 3 instructions Load Register 1, B Add Register 1, C Store Register 1, A RISC:10 instruction Address of B in read register Read B Move data Register 1 Address of C in read register Read C Move data Register 2 Add Register 1, Register 2, Register 3 Move Register 3 to write register Address of A in write register Write A to memory
March 20, 2012
Richard Salomon, Sudipto Mitra (Programming Language Design and Implementation, Prentice Hall, 2000) Copyright Box Hill Institute
CISC Architecture
CISC & RISC Architecture Comparison
It is based on the Von Neumann architecture Motivated by a desire to have low memory bandwidth due to memory being expensive & slow
RISC Architecture
March 20, 2012
It is based on the Harvard Architecture to achieve the goal of one instruction per Richard Salomon, Sudipto Mitra cycle Copyright Box Hill Institute
There
are no commercially available CPUs (computers) that employ a pure RISC architecture Because current technology allows us to place literally millions of transistors on a chip, the best features of both CISC and RISC are employed in modern CPUs
March 20, 2012
Reality Check
Location CPU, Internal, External Capacity usually in bytes Unit of transfer byte or word, usually a multiple of bytes
Access method sequential, direct, random, associative Performance access time, cycle time, transfer rate Physical type semiconductor, magnetic, optical Physical characteristics volatile/non-volatile, erasable, programmable Organisation Physical arrangement of bits into words, not always obvious
Memory Systems - Terminology
March 20, 2012
Memory Hierarchy
March 20, 2012
Memory Hierarchy
March 20, 2012
(Stallings p.101)
Principle of Locality (1)

During the course of the execution of a program, memory references tend to cluster Spatial locality - the tendency to involve a number of clustered memory locations during program execution Temporal locality - the tendency to access memory locations that have been recently used
March 20, 2012
Principle of Locality (2)
March 20, 2012
Main memory
RAM
Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic [ SRAM or DRAM ]
March 20, 2012
Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Level of charge determines value
Dynamic RAM
March 20, 2012
Dynamic RAM Structure
March 20, 2012
DRAM Operation

Address line active when bit read or written Write

Transistor switch closed (current flows)

Voltage to bit line High for 1 low for 0 Then signal address line Transfers charge to capacitor
Read
Address line selected transistor turns on Charge from capacitor fed via bit line to sense amplifier Compares with reference value to determine 0 or 1
Capacitor charge must be restored

March 20, 2012
Static RAM

March 20, 2012
Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Digital - uses flip-flops Cache
Static RAM Structure
March 20, 2012
Both volatile
SRAM v DRAM
Dynamic cell

Power needed to preserve data Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units
Static
Faster Cache
March 20, 2012
Read Only Memory (ROM)

Permanent storage - Nonvolatile Microprogramming Library subroutines Systems programs (BIOS) Function tables
March 20, 2012
Types of ROM

ROM - Written during manufacture, Very expensive for small runs PROM - Programmable (once), Needs special equipment to program Read mostly Erasable Programmable (EPROM), Erased by UV Electrically Erasable (EEPROM), Takes much longer to write than read
Flash memory, Erase whole memory electrically

March 20, 2012
Organisation in detail

A 16Mbit chip can be organised as 1M of 16 bit words A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array Reduces number of address pins
Multiplex
row address and column address 11 pins to address (211=2048) Adding one more pin doubles range of values so x4 capacity
March 20, 2012
Refreshing
Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance
March 20, 2012
Typical 16 Mb DRAM (4M x 4)
March 20, 2012
Packaging
March 20, 2012
Hard Failure
Error Correction
Permanent defect
Soft Error
Random, non-destructive No permanent damage to memory
Detected using CRC or Hamming error correcting code
March 20, 2012
Error Correcting Code Function
March 20, 2012
Basic DRAM same since first RAM chips Enhanced DRAM
Advanced DRAM Organization

Contains small SRAM as well SRAM holds last line read (c.f. Cache!)
Cache DRAM
Larger SRAM component Use as cache or serial buffer
March 20, 2012
Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)
Synchronous DRAM (SDRAM)
March 20, 2012
SDRAM
March 20, 2012
Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package all pins on one side Data exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps Asynchronous block protocol 480ns access time Then 1.6 Gbps
RAMBUS
March 20, 2012
RAMBUS Diagram
March 20, 2012
DDR SDRAM
SDRAM can only send data once per clock Double-data-rate SDRAM can send data twice per clock cycle
Rising edge and falling edge
March 20, 2012
Magnetic Disk Optical
Types of External Memory
RAID Removable
Magnetic Tape
CD-ROM CD-Recordable (CD-R) CD-R/W DVD
March 20, 2012
Magnetic Disk

Disk substrate coated with magnetically sensitive material (iron oxiderust) Substrate used to be aluminium Now glass
Improved surface uniformity, Increases reliability Reduction in surface defects, Reduced read/write errors Lower flight heights Better stiffness Better shock/damage resistance
March 20, 2012
Read and Write Mechanisms

Recording and retrieval via conductive coil called a head May be single read/write head or separate ones During read/write, head is stationary, platter rotates
Write Current through coil produces magnetic field Pulses sent to head Magnetic pattern recorded on surface below
March 20, 2012
Inductive Write MR Read
March 20, 2012
Data Organization and Formatting
Concentric rings or tracks

Gaps between tracks Reduce gap to increase capacity Same number of bits per track (variable packing density) Constant angular velocity
Tracks divided into sectors Minimum block size is one sector May have more than one sector per block
March 20, 2012
Disk Data Layout
March 20, 2012
Disk Velocity

Bit near centre of rotating disk passes fixed point slower than bit on outside of disk Increase spacing between bits in different tracks Rotate disk at constant angular velocity (CAV)

Gives pie shaped sectors and concentric tracks Individual tracks and sectors addressable Move head to given track and wait for given sector Waste of space on outer tracks (Lower data density)
Each zone has fixed bits per track More complex circuitry
Can use zones to increase capacity

March 20, 2012
Disk Layout Methods Diagram
March 20, 2012
Winchester Disk Format Seagate ST506
March 20, 2012
Characteristics
Fixed (rare) or movable head Removable or fixed Single or double (usually) sided Single or multiple platter Head mechanism
Contact (Floppy) Fixed gap Flying (Winchester)
March 20, 2012
Multiple Platters
Tracks and Cylinders

March 20, 2012
Winchester Hard Disk (1)

Developed by IBM in Winchester (USA) Sealed unit One or more platters (disks) Heads fly on boundary layer of air as disk spins Very small head to disk gap Getting more robust
March 20, 2012
Winchester Hard Disk (2)

Universal Cheap Fastest external storage Getting larger all the time
250 Gigabyte now easily available
March 20, 2012
Speed

Seek time
Moving head to correct track

Waiting for data to rotate under head
(Rotational) latency
Access time = Seek + Latency Transfer rate
March 20, 2012
Timing of Disk I/O Transfer
March 20, 2012
Redundant Array of Independent/Inexpensive Disks 6 levels in common use Not a hierarchy Set of physical disks viewed as single logical drive by O/S Data distributed across physical drives Can use redundant capacity to store parity information
March 20, 2012
RAID (1)
RAID (2)

March 20, 2012
RAID0 Data is written to all disk drives RAID1 Data is written to two locations RAID2 Uses a hamming code to create an error correction code RAID3 Uses bit level parity to provide fault tolerance RAID4 Uses block level parity to provide fault tolerance RAID5 Uses block-level parity but spreads or stripes the parity information among all the disk Richard Salomon, Sudipto Mitra
Copyright Box Hill Institute
Two
parity calculations Stored in separate blocks on different disks User requirement of N disks needs N+2 High data availability
Three
RAID 6
disks need to fail for data loss Significant write penalty

March 20, 2012
Optical Storage CD-ROM

Originally for audio 650Mbytes giving over 70 minutes audio Polycarbonate coated with highly reflective coat, usually aluminium Data stored as pits Read by reflecting laser Constant packing density Constant linear velocity
March 20, 2012
CD Operation
March 20, 2012
CD-ROM Drive Speeds
Audio is single speed Constant linear velocity 1.2 ms-1 Track (spiral) is 5.27km long Gives 4391 seconds = 73.2 minutes Other speeds are quoted as multiples e.g. 24x Quoted figure is maximum drive can achieve
March 20, 2012
CD and DVD
March 20, 2012
Magnetic Tape
Serial access Slow Very cheap Backup and archive
March 20, 2012
What Is Virtual Memory?

If you think its there, and its thereits real. If you think its not there, and its thereits transparent. If you think its there, and its not thereits imaginary. If you think its not there, and its not thereits nonexistent.
Virtual memory is imaginary memory: it gives you

the illusion of a memory arrangement thats not physically there.
(Virtual Memory, CS 105, Tour of the Black Holes of Computing!)
March 20, 2012
Virtual Memory (1)

Use of main memory and disk space to provide the illusion of endless amount of physical memory. Memory on hard disk Allows for effective multiprogramming and relieves the user of tight constraints of main memory
March 20, 2012
Virtual Memory (2)
Invented to solve problem that a program or collection of ready programs are larger than physical memory Before virtual memory, overlays were used

March 20, 2012
Programmer splits program into swap units called overlays Overlays must not refer to memory addresses outside of itself except through special call to ask OS to specifically swap 2 swap units Unfriendly programming model
(Virtual Memory, ICS 143) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Virtual Memory (3)
Virtual memory range of addressable locations independent of size of physical memory Each process given a separate virtual address space
Similar to having separate memory partitions for each process, but virtual address space is not physically bounded Instead, virtual address space is limited by memory address size Dependent on architecture 32-bit address was typical (232 = 4 billion) 64-bit is becoming more prevalent (264 = 16 quintillion)
Richard Salomon, Sudipto Mitra (Virtual Memory, ICS 143) Copyright Box Hill Institute
March 20, 2012
Virtual Memory (4)
Virtual address space often divided into a few large regions that are used differently Entire virtual address space is not addressable by a process Off-limit regions used by OS to store per-process data structures Virtual memory is a form of indirect addressing
March 20, 2012
A System with Physical Memory Only

Memory
Physical Addresses 0: 1:
CPU
N-1:

Addresses generated by the CPU correspond directly to bytes in physical memory Examples include, Most Cray machines, early PCs, some embedded systems
March 20, 2012
(Virtual Memory, CS 105, Tour of the Black Holes of Computing!) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Virtual Memory Mapping
Memory management unit (MMU)
Hardware to map virtual address to physical address Hardware essential for performance MMU resides in the CPU package MMU sends translated physical memory address onto memory bus
Steps in virtual address translation

1) 2)
3)
CPU issues a program instruction MMU translates virtual address to physical (main memory) address (not physical location on disk!) Physical memory page frame is accessed
March 20, 2012
A System with Virtual Memory

Memory
Page Table
Virtual Addresses 0: 1: Physical Addresses
0: 1:
CPU
P-1:
N-1: Disk
Address Translation: Hardware converts virtual addresses to physical addresses via OS-managed lookup table (page table) March 20, 2012 Examples include, Workstations, servers,Mitra Richard Salomon, Sudipto modern PCs, etc.
(Virtual Memory, CSCopyright Box Hill Institute Holes of Computing!) 105, Tour of the Black
Cache
Relatively small amount of very fast SRAM Holds current working set of memory pages More on cache next week
March 20, 2012
Summary

Spatial locality, Temporal locality A Static Ram stores bits as on/off switches A Dynamic RAM stores bits as charge in capacitors RAID is a set of physical disks viewed as single logical drive by the operating system Use of main memory and disk space to provide the illusion of endless amount of physical memory
March 20, 2012
Reference
Stallings William, 2003, Computer Organization & Architecture designing for performance, 6th edn, Pearson Education, Inc. ISBN 0-13-049307-4 [chapter 4, 5 & 6] Virtual Memory, ICS 143 Virtual Memory, CS 105, Tour of the Black Holes of Computing!
March 20, 2012
Internet Resources
Optical Storage Technology Association

Good source of information about optical storage technology and vendors Extensive list of relevant links
DLT tape - Good collection of technical information and links to vendors Search on RAID
March 20, 2012

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Centre for Computer Technology

ICT123 Computer Architecture

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

CISC vs RISC (1)

CISC & RISC Architecture Comparison

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Memory Systems - Terminology

March 20, 2012

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Principle of Locality (1)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Principle of Locality (2)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Dynamic RAM Structure

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Address line active when bit read or written Write

Transistor switch closed (current flows)

Capacitor charge must be restored

March 20, 2012

March 20, 2012

Static RAM Structure

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Read Only Memory (ROM)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Flash memory, Erase whole memory electrically

March 20, 2012

March 20, 2012

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Typical 16 Mb DRAM (4M x 4)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Detected using CRC or Hamming error correcting code

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Error Correcting Code Function

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Basic DRAM same since first RAM chips Enhanced DRAM

Advanced DRAM Organization

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Synchronous DRAM (SDRAM)

March 20, 2012

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute