Ict123 W7

Centre for Computer Technology
ICT123 Computer Architecture

Week 07
RISC Architecture (Comparison with CISC)
Objectives
A brief overview of week6 RISC Architecture CISC Architecture CPU Registers and Cache Superscalar Comparison
March 20, 2012
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Timing of Pipeline
March 20, 2012
Pipelining
30 A B C D
Multiple tasks operating simultaneously using different resources
March 20, 2012
40
40
40
40 20
(Dr. John Kubiatowicz, UC Berkeley) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Alternative Pipeline Depiction
March 20, 2012
Dealing with Branches

Multiple Streams Prefetch Branch Target Loop buffer Branch prediction Delayed branching
March 20, 2012
Branch Prediction Flowchart
March 20, 2012
Branch Prediction State Diagram
March 20, 2012
RISC architecture attempts to:

Remove seldom used complex instructions Maintain a set of simple, fast instructions Ensure uniform instruction execution time Allow only data transfer operations
between the CPU and other system components Perform data changing operations only in the CPU
March 20, 2012
RISC Characteristics
Simple fixed length instructions that
execute in the same short time
A large set of CPU data registers used
for
data storage parameter passing

March 20, 2012
RISC History : Early Development

Late 1970s, IBM, John Cocke, 801 design 1980, Berkeley Uni + DARPA, David Patterson, RISC-I and RISC-II 1981, Stanford Uni + DARPA, John Hennessy, MIPS 1986, Hennessy founds MIPS company 1987, SUN Microsystems SPARC based on Berkeley RISC-II machine
March 20, 2012
What is RISC ?
Introduction
March 20, 2012
RISC stands for Reduced Instruction Set Computer RISC processors have simpler types of instructions than CISC CISC stands for Complex Instruction Set Computer RISC computers are optimized to reduce the number of cycles per instruction Instruction Pipelining Sudipto Mitra More Registers Richard Salomon,Hill Institute Copyright Box
Introduction - RISC
Simple address modes Simpler is better - easier design (& less time) Save space - simpler means smaller & faster Smaller means less heat Load/Store architecture Uniform instruction length Instruction pipelining
March 20, 2012
Introduction CISC (1)

Richer instruction set, some simple, some very complex Instructions generally take more than 1 clock to execute Instructions of a variable size Instructions interface with memory in multiple mechanisms with complex addressing modes Microcode control No pipelining
(Yi gao, Shilang Tang, Zhongli Ding) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
March 20, 2012
Introduction CISC (2)

Works well with simpler compiler Segmented memory model Few registers Unsatisfactory floating point performance Upward compatibility within a family
(Yi gao, Shilang Tang, Zhongli Ding)

March 20, 2012
For example: A=B+C
Alternative - RISC
CISC: 3 instructions Load Register 1, B Add Register 1, C Store Register 1, A RISC:10 instruction Address of B in read register Read B Move data Register 1 Address of C in read register Read C Move data Register 2 Add Register 1, Register 2, Register 3 Move Register 3 to write register Address of A in write register Write A to memory
March 20, 2012
(Programming Language Design and Implementation, Prentice Hall, 2000) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
CISC Architecture
CISC & RISC Architecture Comparison
It is based on the Von Neumann architecture Motivated by a desire to have low memory bandwidth due to memory being expensive & slow
RISC Architecture
March 20, 2012
It is based on the Harvard Architecture to achieve the goal of one instruction per Richard Salomon, Sudipto Mitra cycle Copyright Box Hill Institute
CISC Architecture
Main Memory
Cache
Instructions/Data
Processor Microprogrammed CPU ROM

March 20, 2012
RISC Architecture

Independent paths for instructions & data Control Unit can be hardwired due to low number of simple operations. Less processing logic.
Data Cache (Data) Data Main Memory Cache (Instructions)
Processor (hardwired)
Instructions
March 20, 2012
Instructions
RISC Attributes (1)

A low number of addressing modes A simplified instruction format Single cycle execution of all instructions Memory access to be performed by LOAD/STORE instructions only The CPU has a relatively large register set.
March 20, 2012
RISC Attributes (2)

Most operations are Register to Register Support for High Level Languages (HLL) Harvard Architecture to allow for more memory bandwidth Simpler instructions that are easy to decode and execute quickly
March 20, 2012
Elements of Processor design

March 20, 2012
Prefetching and Cache Registers Superscalar (multiple execution units) Pipelining / Stalls Reordering (Out-of-Order execution) Branch Prediction Code Creep (Code Bloat)
Prefetching & Cache

Prefetching data is a way to "guess" at what the processor is going to need, and loading it ahead of time. Cache could improve speed on loading (prefetch), reloading (cache) and storing (deferred writing).
March 20, 2012
IBM 801 interconnections

External Bus
CPU
32 Data Cache 32 Internal Buses 32
Instruction Cache 32
I/O Adaptors
To I/O devices
Main Memory
M- I/O Bus
March 20, 2012
Large Register File

All local scalars
Registers v Cache
Cache
Recently used local scalars Individual variables Blocks of memory Compiler assigned global variables Recently used global variables Save/restore based on procedure Save/restore based on nesting caching algorithm Register addressing Memory addressing
(W Stallings)
March 20, 2012
Registers
More registers help with performance Programs are often loading, unloading and overwriting these locations sometimes too soon With more registers you keep the data longer which can mean increased performance
March 20, 2012
RISC Registers : Berkeley RISC II

The CPU has a total of 138, 32 bit registers Registers are numbered R0 to R137 A program or procedure sees only 32 registers Multiple registers are used for parameter passing between calling & called procedures and for storage of local variables by each procedure
March 20, 2012
More Registers
Global Registers R0 to R9
Window Registers R10 to R31 are seen by each procedure

R26 to R31 Parameters passed to this procedure by the calling procedure R16 to R25 Local scalar variables of this procedure R10 to R15 Parameters passed by this procedure to the called procedure
Are seen by all procedures, and are used to store global program variables.
March 20, 2012
CPU Registers (1)

R31 R26 R25 Window Registers R16 R15 LOW R10 R9 HIGH LOCAL
GLOBAL
March 20, 2012
R0
CPU Registers (2)

There are a total of 8 windows Each window is identified by a window number 0 to 7. Stored in CWP. CPU working registers are identified by an Address Pair :
Window number . Register number eg window 7 and register 10 is 7.10

March 20, 2012
CPU Registers (3)

R137 R132 R131 R122
HIGH
LOCAL
LOW HIGH LOCAL LOW HIGH LOCAL LOW
R9
Global
March 20, 2012
A Global
B Global
C C Global
R0
Register Windows cont.
Three areas within a register set

Parameter registers Local registers Temporary registers Temporary registers from one set overlap parameter registers from the next This allows parameter passing without moving data
March 20, 2012
(W Stallings) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Overlapping Register Windows
(W Stallings)
March 20, 2012
Circular Buffer diagram
(W Stallings)
March 20, 2012
Operation of Circular Buffer

When a call is made, a current window pointer is moved to show the currently active register window If all windows are in use, an interrupt is generated and the oldest window (the one furthest back in the call nesting) is saved to memory A saved window pointer indicates where the next saved windows should restore to
March 20, 2012
Richard Salomon, Sudipto Mitra (W Stallings) Copyright Box Hill Institute
Superscalar (1)
Allow more things to happen at once Add extra execution units Instructions could be interwoven so that each execution unit could be kept busy Superscalar means that more work can get done at the same time
March 20, 2012
Superscalar (2)
PowerPC G4 processor:
The Branch Unit dispatches up to the 3 main execution units. Each of these has its own register sets. Up to 3 instructions can be issued per cycle: a branch and 2 instructions to any 2 separate execution units. Sudipto Mitra Richard Salomon,
March 20, 2012
Copyright Box Hill Institute
CISC IBM 370/168 1973 DEC VAX Intel 11/780 486 1978 1989
RISC Motorola MIPS 88000 R4000 1988 1991
Superscalar IBM Intel RS/6000 80960 1990 1989
No. of instruction 208 303
235
51
94
184
62
Instruction size (octets) 2-6 2-57 1-11 Addressing modes 4 22 GP Registers 16 16
32
4 or 8
11
11
32
32
32
23-256
Control memory (k bytes) (microprogramming) 420 480 246

March 20, 2012
(W Stallings) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Cache Stalls
If you have a pipe, and one of the stages is dependent on another instructions data and the instruction hasn't been completed, then the process stalls.
March 20, 2012
Reordering (Out-of-Order execution)

Reordering is very complex, and it can only work in certain cases, but it is one way to reduce the pain of pipe-stalls.
March 20, 2012
Branch instructions (conditionals) stall the process Prediction tries to guess which data or commands will be required next Development:
Compiler bit was set to the most often used path Then set to go the same way next time Load both options - then discard the wrong one
March 20, 2012
Branch Prediction (Out of Order execution)
Code Creep (Code Bloat)

CISC instructions are variable in size, and work with different sized data. CISC instructions don't take any more memory than they absolutely have to. RISC instructions have all instructions the same size. So the data and instructions aren't as packed (efficient).
March 20, 2012
RISC Instructions (1)

RISC I has 31 instructions RISC II has 39 instructions Integer Add instruction example:
ADD Rs, S2, Rd Rd <- Rs+S2 Add the contents of the source register Rs to S2 a CPU register or a constant, store result to destination register Rd
March 20, 2012
RISC Instructions (2)

Synthesis of Common Instructions
Register Move
Move Rs, Rd ADD Rs, R0, Rd Rd :=(Rs) + 0
Clear Register
CLR Rs, S2 ADD R0, R0, Rd ADD R0, R0, R0 Rd := 0 + 0 R0 := 0 + 0
NOP
NOP
March 20, 2012
Typical RISC Machine
HP 3000 Precision Architecture

140 instructions Single cycle instruction execution 32 general purpose registers 3 Stage instruction pipeline (fetch, Execute & Store)
March 20, 2012
HP 3000 Processor Module

Instruction Unit Execution Unit Instruction Decoding. Sequencing. and Control
ALU
Shifter Floating Point Coprocessor
Register
File
Instruction Cache. 64 Kb
March 20, 2012
Data Cache. 64 Kb
BUS
Pentium II vs the PowerPC G3

PowerPC G3 is on the left Pentium II is on the right G3 processor is small black square Pentium II is about the size of the hologram Note heat sink size of both
March 20, 2012
RISC vs CISC Comparison

RISC
Instruction set Instr. length Instr. exec. time Register set Function call small fixed short large fast
CISC
large variable variable small slow
March 20, 2012
Current Development
More transistors means less need for tight design More complex single-stream processors
more parallelism in a single core get the processor to do more in each cycle
Simpler multi-stream processors.

add more cores and execution units
RISC and CISC convergence

designers will use the best mix of techniques
March 20, 2012
There are no commercially available CPUs (computers) that employ a pure RISC architecture Because current technology allows us to place literally millions of transistors on a chip, the best features of both CISC and RISC are employed in modern CPUs Now we can investigate the CISC vs RISC story in more detail
March 20, 2012
Reality Check
Summary
RISC is a philosophy with the goal to reduce the COMPLEXITY in the processor Using your CORE space more wisely Simpler instructions = easier design Easier design = faster to market
March 20, 2012
References

Stallings William, 2003, Computer Organization & Architecture designing for performance, 7th edn, Pearson Education, Inc. D.Tabak, RISC Architecture, Research Studies Press, 1987 A.J. van de Goor, Computer Architecture and Design, Addison-Wesley, 1989 Computer System Architecture, M Morris Mano, 3rd edn, Prentice Hall. A.L.Decegama, The Technology of Parallel Processing, Prentice-Hall, 1989 K.Dowd & C.R. Severance , High Performance Computing, OReilly, 1998
March 20, 2012
References

March 20, 2012
RISC Machines, Ric Giaquinta, Graeme Brokenshire, Abele Woldekidan Comparison Between CISC and RISC, Yi gao, Shilang Tang, Zhongli Ding, May 2000 http://www.mackido.com http://www.cs.washinton.edu/homes/lazowaska/cra/ris c.html http://www.pcmech.com/cpuhistory.html http://www.lightner.net/lightner/zen.html http://gene.wins.uva.nl/~djakman/Paper_APR.html http://thetech.pcwebopedia.com/TERM/m/microproces sor.html

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Centre for Computer Technology

ICT123 Computer Architecture

RISC Architecture (Comparison with CISC)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Alternative Pipeline Depiction

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Dealing with Branches

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Branch Prediction Flowchart

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Branch Prediction State Diagram

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

RISC architecture attempts to:

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

execute in the same short time

A large set of CPU data registers used

data storage parameter passing

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

RISC History : Early Development

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Introduction CISC (1)

March 20, 2012

Introduction CISC (2)

(Yi gao, Shilang Tang, Zhongli Ding)

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

For example: A=B+C

CISC & RISC Architecture Comparison

March 20, 2012

Processor Microprogrammed CPU ROM

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

RISC Attributes (1)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

RISC Attributes (2)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Elements of Processor design

Prefetching & Cache

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

IBM 801 interconnections

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Large Register File

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

RISC Registers : Berkeley RISC II

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Window Registers R10 to R31 are seen by each procedure