Ict123 W4

Centre for Computer Technology
ICT123 Computer Architecture

Week 04 CPU - System Architecture and Organization
Content at a Glance
Week 3
integer and floating point number representation review Logic circuit building blocks CPU Structure and architecture Component and System buses Von Neumann and wider architectures
March 20, 2012
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Integer data interpretation

The
machine does not care about nor does it attempt to interpret the data it holds. It is the programmers responsibility to interpret the stored bit pattern data. However, the machine provides support to enable signed and unsigned interpretation all processed data.
March 20, 2012
Integer data subtraction
so
A B = A + [ -B ] i.e. 2s comp addition 6 -2 --8 0110 6 0110 0010 becomes + [-2] 1110 ---------- ------1000 4 0100
March 20, 2012
Integer data limitation

Range
bits n 8 16 32 64
unsigned 2n-1 0 to 255 0 to 65,535 4.2949 * 109 1.84467 * 1019
signed (2sComp) -2n-2 to + (2n-21) - 128 to +127 -32768 to +32767 2.14748 * 109 9.223 * 1018
March 20, 2012
Floating Point data

Floating
point data representation allow us to store fractional numbers, and is modelled on scientific notation. e.g.1: (+) 3.5 * 102 [ 350 ] e.g.2: - 25 * 10-3 [ - 0.025 ]
We
can store floating point numbers in three parts, namely: sign, significant, exponent The same applies to binary numbers
March 20, 2012
IEEE754 Standard
Single precision numbers are stored in 32-bit normalized binary format:

msb
lsb
8 bits biased exponent
23 bits Significand In a normalized binary number the msd is 1, which
March 20, 2012
Sign of significand 0 positive 1 negative
is implied (not stored).
Single Precision Number range

-
(2 2-23 ) * 2128 to -2-127 and 2-127 to (2-2-23) * 2128

There
is a small number range near (and including) zero which can not be represented in the normalized format. This is known as underflow. Zero is treated as a special case
March 20, 2012
Expressible Numbers
(Stallings p.310)
March 20, 2012
Double precision numbers are stored
IEEE754 Standard
in 64-bit normalized binary format: lsb msb 1 11 bits biased exponent 52 bits Significand In a normalized binary number the msd is 1, which is implied (not stored).
Sign of significand 0 positive 1 negative

March 20, 2012
Floating Point data Arithmetic

Floating point
arithmetic operations performed by numeric data processors (co-processors) are: addition subtraction multiplication and division
March 20, 2012
Floating Point Addition / Subtraction

In
addition and subtraction it is necessary to have both operands with the same exponent value
1. 2.
3. 4.
The steps in are: check for zero values denormalize significant and equalize exponent values add/subtract the significant values normalize the result
March 20, 2012
Floating Point Multiplication / Division

Floating
point multiplication and division are simpler than addition and subtraction because the is no need to align exponents
The
steps in are: 1. check for zero values 2. add/subtract exponents 3. check for errors 4. multiply/divide significands 5. normalize 6. round
March 20, 2012
Guard bits and rounding

all
arithmetic operations suffer from rounding errors rounding errors occur because we cant represent all values exactly, so we approximate their values
March 20, 2012
guard
bits are additional bits attached to the rhs of the significand guard bits help to retain accuracy in the final result
NaN
NaN is
a symbolic quantity encoded in floating point numbers for a result which can not be represented in the available space or format e.g. result, or meaningless result from 0/0, / , or 0*
March 20, 2012
Binary Digital Logic

Binary
logic supports two conditions; true (T) and false (F) These conditions are represented by two distinct voltage levels; VH or 1, and VL or 0 There are three fundamental logic operators: AND (coincidence), OR (selection), NOT (negation or complement) All logic conditions can be met by expressions using a combination of the above three operations
March 20, 2012
Digital Logic Gates
XOR XOR gate
March 20, 2012
Basic 1 bit Memory

SC Latch
D Latch
March 20, 2012
D Latch (Transparent Latch)
March 20, 2012
Memory cell
n-bit Register
Dn D EN clk Qn
March 20, 2012
D1 Q D EN Q
D0 D EN Q
Q1
Q0
Adder- Subtractor
March 20, 2012
(Stallings)
Adder Subtractor (Data Paths/Hardware Elements)

Central
Element is a Binary Adder. The two numbers (integers) are treated as Unsigned Numbers. The two numbers are presented to the adder from two registers. The result is stored in one of the registers or a third. Overflow is stored in an Overflow Flag.
March 20, 2012
(Stallings) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Computer Components: Top Level View
March 20, 2012
Computer System Modules
March 20, 2012
Data Exchanges
Memory
to Processor Processor to Memory I/O to Processor Processor to I/O I/O to or from Memory
March 20, 2012
Buses
A
bus is a group of parallel conductors Carry information from one part of a computer to another. Four Types - Address bus, Data bus, Control bus, Power bus Bus pins are sometimes shared in order to reduce the overall size of the IC. This sharing of pins is achieved by switching or multiplexing.
March 20, 2012
Types of Buses
Address
buses, send address information to memory and other devices. Data buses carry data in and out of the processor. Control buses carry supervisory signals such as clocks, interrupts, read / write etc. Power bus, does not carry information. They Transmit DC and ground voltages. Generally not considered a bus.
March 20, 2012
Bus Architecture
March 20, 2012
March 20, 2012
Bus Interconnection Schemes

Single System Bus
March 20, 2012
Physical Realization of Bus Architecture
March 20, 2012
Single Bus Problems

Lots
Propagation
Long
of devices on one bus leads to:

delays
data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity
Most
systems use multiple buses to overcome these problems

March 20, 2012
Traditional (ISA) (with cache)
March 20, 2012
High Performance Bus
March 20, 2012
Type
Elements of Bus Design

Bus Width
Address Data
Dedicated Multiplexed
Method of Arbitration
Centralized Distributed
Data Transfer Type

Read Write Read Modify Write Read After Write Block
Timing
Synchronous Asynchronous March 20, 2012
Multiplexing
Shared lines Address valid or data valid control line Disadvantages
More complex control Ultimate performance

March 20, (W Stallings) 2012
Synchronous Timing Diagram
March 20, 2012
CPU Read / Write
March 20, 2012
Asynchronous Timing Diagram
March 20, 2012
CPU Read / Write
March 20, 2012
Processor Organization
Fetch
Instruction Read instruction from memory Interpret Instruction Decode instruction Fetch Data Read data from memory Process Data Perform an arithmetic or Logic operation on the data Write Data Write data to memory or I/O module
March 20, 2012
CPU With Systems Bus
March 20, 2012
CPU Internal Structure
March 20, 2012
Register Organization(1)
Computer System uses
hierarchy. The higher levels of memory are faster, smaller and more expensive (per bit). In the processor, the registers are above the main memory and cache in the hierarchy.
March 20, 2012
a memory
Register Organization(2)
The registers
two functions User-visible registers, enable the programmer to optimize main memory references by using registers Control and Status registers, used by control unit to control the processor or the execution of programs.
March 20, 2012
in the processor perform
User Visible Registers

General
Purpose Registers Assigned to a variety of functions by the programmer Data Registers Used to hold data Address Registers Devoted to a particular addressing mode. Examples are
Segment
Condition
Codes (Flags) Hold conditions. Set by the processor hardware as a result of operations.
Pointers Index Registers Stack Pointer
March 20, 2012
Control and Status Registers

Program
Counter (PC) Contains the address of an instruction to be fetched. Instruction Register (IR) Contains the instruction most recently fetched. Memory Address Register (MAR) Contains the address of a location in memory. Memory Buffer Register (MBR) Contains a word of data to be written to the memory or the word most recently read.
March 20, 2012
Program Status Word (PSW)

PSW
contains condition codes (flags) and other status information. Examples are
Sign Zero Carry Equal Overflow Interrupt
Enable/Disable Supervisor (indicates if the processor is operating in supervisor or user mode)

March 20, 2012
Examples Register Organizations(1)
March 20, 2012
Examples Register Organizations(2)
MC68000 32 bit registers, partitioned into eight data registers and nine address registers. Two registers are used as stack pointers. 32 bit program counter 16 bit status register
March 20, 2012
Intel 8086 Four 16 bit data registers and four 16 bit pointer/index registers Three pointer/index registers are dedicated to point to the segment and current instruction Includes an Instruction Pointer and 1 bit status/control flags.
Pentium Registers(1)
March 20, 2012
Pentium Registers(2) Tag Word

It
is a 16 bit register contains a 2 bit tag for floating point numeric registers. The tags enable to check the contents. There are four possible values
Valid Zero
Special Empty
March 20, 2012
(NaN, infinity, denormalised)

Pentium EFLAGS Register(1)
March 20, 2012
Pentium EFLAGS Register(2)

The EFLAGS
register indicates the condition of the processor. It includes six condition codes
Carry Parity Zero Sign
March 20, 2012
Auxiliary
Overflow
Pentium MMX Registers(1)

Introduced by
Intel in 1996 MMX is a set of highly optimized instructions for Multimedia tracks. MMX uses a 3 bit register address fields so that eight 64 bit MMX registers are supported. The existing floating register is used to store the MMX values.
March 20, 2012
Pentium MMX Registers(2)
Mapping of MMX Registers to Floating-Point Registers
March 20, 2012
PowerPC User Visible Registers(1)
March 20, 2012

General
Registers thirty two 64 bit registers. (load, store, manipulate data) Exception Register (XER) report exceptions in integer arithmetic operations Floating Point Status and Control register (FLSCR) operations of the floating point unit.
March 20, 2012

Condition
Register condition code fields Link Register indirect addressing of target address call/return behavior. Count control an iteration loop indirect addressing of target address
March 20, 2012
PowerPC Register Formats
March 20, 2012
Summary
Boolean Logic, System Buses Dedicated and
Simple Memory Element
Multiplexed Buses Bus Interconnection to optimize performance Register Organization Pentium Registers Power PC Registers
March 20, 2012
Reference
Stallings
William, 2003, Computer Organization & Architecture designing for performance, 7th edn, Pearson Education Computer System Architecture, Frank Duyker, Box Hill TAFE
March 20, 2012
Further Reading
Manufacturers
websites Relevant Special Interest Groups [SIG] www.pcguide.com/ref/mbsys/buses/ www.pcguide.com/
March 20, 2012

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Centre for Computer Technology

ICT123 Computer Architecture

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Integer data interpretation

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Integer data subtraction

March 20, 2012

Integer data limitation

unsigned 2n-1 0 to 255 0 to 65,535 4.2949 * 109 1.84467 * 1019

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Floating Point data

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Single precision numbers are stored in 32-bit normalized binary format:

8 bits biased exponent

23 bits Significand In a normalized binary number the msd is 1, which

March 20, 2012

Sign of significand 0 positive 1 negative

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

is implied (not stored).

Single Precision Number range

(2 2-23 ) * 2128 to -2-127 and 2-127 to (2-2-23) * 2128

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Double precision numbers are stored

Sign of significand 0 positive 1 negative

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Floating Point data Arithmetic

March 20, 2012

Floating Point Addition / Subtraction

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Floating Point Multiplication / Division

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Guard bits and rounding

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Binary Digital Logic

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Digital Logic Gates

XOR XOR gate

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Basic 1 bit Memory

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

D Latch (Transparent Latch)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Adder Subtractor (Data Paths/Hardware Elements)

(Stallings) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Computer Components: Top Level View

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Computer System Modules

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute