Low Power CMOS VLSI Circuit Design (LPVD)

Dr. Veena S Chakravarthi

Goal of the Course

To understand the need for low power from device/technology point of view of VLSI designs, Basic idea/concepts of low power, estimating power consumption and power optimization design methodology for VLSI chips.

Agenda
UNIT 1
Introduction : Need for low power VLSI chips, Sources of

power dissipation on Digital Integrated circuits. Emerging Low power approaches, Physics of power dissipation in CMOS devices.
Device & Technology Impact on Low Power: Dynamic

UNIT 2

dissipation in CMOS, Transistor sizing & gate oxide

thickness, Impact of technology Scaling, Technology & Device innovation
Power estimation, Simulation Power analysis: SPICE circuit

simulators, gate level logic simulation, capacitive power

UNIT 3

estimation, static state power, gate level capacitance estimation, architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation.

Agenda
Probabilistic power analysis: Random logic signals,

UNIT 4

probability & frequency, probabilistic power analysis

techniques, signal entropy.

Low Power Design Circuit level: Power consumption in

UNIT 5

circuits. Flip Flops & Latches design, high capacitance nodes, low power digital cells library

UNIT 6

Logic level: Gate reorganization, signal gating, logic

encoding, state machine encoding, pre-computation logic

Agenda
Low power Architecture & Systems: Power & performance

UNIT 7

management, switching activity reduction, parallel

architecture with voltage reduction, flow graph transformation, low power arithmetic components, low power memory design.
Low power Clock Distribution: Power dissipation in clock

UNIT 8

distribution, single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip & package co design of clock network
Algorithm & Architectural Level Methodologies: Introduction,

UNIT 9

design flow, Algorithmic level analysis & optimization, Architectural level estimation & synthesis.

Reference Books
1. Kaushik Roy, Sharat Prasad, Low-Power CMOS VLSI Circuit Design Wiley, 2000 2. Gary K. Yeap, Practical Low Power Digital VLSI

Design, KAP, 2002

3. Rabaey, Pedram, Low Power Design Methodologies Kluwer Academic, 1997

4. Web materials

ISSCC, Feb. 2001, Keynote

Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second about the same number of calculations that the world's fastest supercomputer can perform now.
Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP.

Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .

Curtosy: Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 1

Latest News
Power management, 2011 Jack Ganssle 1/30/2011
From Microchip's eXtreme Low Power to TI's OMAP, new chips contain some interesting and complex power management techniques. http://www.eetimes.com/discussion/break-points/4212679/Powermanagement--2011

VLSI Chip Power Density

10000 Power Density (W/cm2)

Suns Surface Rocket Nozzle Nuclear Reactor

8086

1000

100

Hot Plate
P6 Pentium 486 1990 Year 2000 2010
9

10 4004 8008 8085 386 286 8080 1

1970 1980

Source: Intel

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 1

SIA Roadmap for Processors (1999)

Year
Feature size (nm) Logic transistors/cm2 Clock (GHz) Chip size (mm2) Power supply (V) High-perf. Power (W)

1999
180 6.2M 1.25 340 1.8 90

2002
130 18M 2.1 430 1.5 130

2005
100 39M 3.5 520 1.2 160

2008
70 84M 6.0 620 0.9 170

2011
50 180M 10.0 750 0.6 175

2014
35 390M 16.9 900 0.5 183

Source: http://www.semichips.org
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 10

Power values of processors [ISSCC]

Problems found on first spin of silicon in 180/130 nm

Trends in Power conumption

Trends in power components

Component 90nm 65nm 1.4X 45nm 2X

Dynamic Power 1X per sq.cm

Static Power per sq. cm

1X

2.5X
2X

6.5X
4X

Total Power per 1X sq.cm

Dynamic vs Static power

Sources of Power Consumption

Logic transitions
PD proportional to V, voltage swing, av. Switched capacitance/cycle

n-subnetwork and p-subnetwork conducting simultaneously.

Depends on input-output transitions

When input to and output from are not changing

Current flow when ip is stable.

Designing for Low power

Reducing supply voltage Reducing Vt Frequency of transition or probability of transition.

MIS Structure as a tool to study surfaces

y

Metal

Insulator

Semiconductor- p-type

MOS (Metal-Oxide-Semiconductor)

Assume work function of metal and semiconductor are same.

MOS materials

MOS structure

Shown is the semiconductor substrate with a thin oxide layer and a top metal contact, also referred to as the gate. A second metal layer forms an Ohmic contact to the back of the semiconductor, also referred to as the bulk. The structure shown has a p-type substrate. We will refer to this as an n-type MOS capacitor since the inversion layer contains electrons.

Terminologies
Workfunction:
electron in metal vacuum system to escape into vacuum from an initial energy at a fermi level. In metal semiconductor system, still it can be used by replacing free space permittivity 0 semiconductor permittivity s

Minimum energy necessary for a metal

Electron Affinity: Bandgap:

electron at the vacuum level and electron at the bottom of the conduction band.

The difference in potential between an

valence band and the bottom of the conduction band in the semicondutor Eg

Is the the energy difference between the top of the

Energy bandgap (Eg) in semiconductor

Structure and principle of operation

To understand the different bias modes of an MOS we consider 3

different bias voltages.

below the flatband voltage, VFB between the flatband voltage and the threshold voltage, VT, and larger than the threshold voltage.

These bias regimes are called the accumulation, depletion and inversion mode of operation.

Structure and principle of operation

Charges in a MOS structure under accumulation, depletion and inversion conditions

Four modes of MOS operation

The four modes of operation of an MOS structure:
Flatband, Depletion, Inversion and Accumulation.

Flatband conditions exist when no charge is present in the semiconductor so that the Si energy band is flat. Surface depletion occurs when the holes in the substrate are pushed away by a positive gate voltage. A more positive voltage also attracts electrons (the minority carriers) to the surface, which form the so-called inversion layer. Under negative gate bias, one attracts holes from the p-type substrate to the surface, yielding accumulation

Effects of Real Surfaces

Charge Distribution

Key Definitions

Potential Definition

Depletion Width

Gate Voltage (depletion case)

MOS capacitor structure

MOS capacitor- accumulation

MOS capacitor- accumulation

Accumulation occurs typically for -ve voltages where the -ve charge on the gate attracts holes from the substrate to the oxide-semiconductor interface. Depletion occurs for positive voltages. The +ve charge on the gate pushes the mobile holes into the substrate. Therefore, the semiconductor is depleted of mobile carriers at the interface and a -ve charge, due to the ionized acceptor ions, is left in the space charge region.

MOS capacitor- flat band

MOS capacitor- flat band

The voltage separating the accumulation and depletion regime is referred to as the flatband voltage, VFB. The flatband voltage is obtained when the applied gate voltage equals the workfunction difference between the gate metal and the

semiconductor.
If there is a fixed charge in the oxide and/or at the oxide-silicon interface, the expression for the flatband voltage must be modified accordingly.

MOS capacitor- depletion

MOS capacitor- inversion