Logic and Computer Design Fundamentals

Chapter 8 Register Transfer Level Design

Overview
 Register Transfer Level(RTL)  Algorithmic State Machines (ASM)

Chapter 8 - Fall 10

Register Transfer Level (RTL)

 A digital system is a sequential logic system.  It is designed via modular approach.  The system is divided into modules and modules contain registers, multiplexers, decoders and control logic.  The modules are defined by a set of registers and the operations done on the binary information stored in these registers.
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Register Transfer Level (RTL)

 A digital system is represented at the register transfer level (RTL) when it is specified by the followingcomponents:
The set of registers in the system The operations that are performed on the data stored in the registers The control that supervises the sequence of operations in the system

Chapter 8 - Fall 10

Register Transfer Level (RTL)

 The operations executed on the information stored in registers are elementary operations. They are performed in one clock cycle.  The information in a register may be replaced by an operation .  The result in a register may be transferred into another register.  The operations performed are controlled by timing signals that sequence the operations in a prescribed manner.
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Register Transfer Level (RTL)

 Information transfer from one register to another is shown as R1 R2.  Which means replace the information in register R1 by contents of register R2.  A control signal will determine when the operation is executed.  If(T1=1) R1 R2 is a conditional transfer which will take place when T1=1.  If no condition is specified the operation is done with clock transition.
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Register Transfer Level (RTL)

Some examples of register transfers:  R1 R2+R3. (R2 and R3 are connected to inputs of an adder and R1 is connected to the output of an adder)  T2: R1 R1+1 (R1 can be incremented by some logic)  R2 shr R3 (Shift the information in R3 right, and transfer the information to R2)  If(T1=1) R1 R2 & R1 Bitwise and operation when T1=1  R2 0 Clear operation. R1 Datain External data transferred into R1
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Logical Microoperations
 From Table 7-4:
Symbolic Designation R0 n R1 R0 n R1 R2 R0 n R1 R2 R0 n R1 R2 Description Bitwise NOT Bitwise OR (sets bits) Bitwise AND (clears bits) Bitwise EXOR (complements bits)

Chapter 8 - Part 1

Logical Microoperations (continued)  Let R1 = 10101010, and R2 = 11110000  Then after the operation, R0 becomes:
R0 01010101 11111010 10100000 01011010 Operation R0 n R1 R0 n R1 R2 R0 n R1 R2 R0 n R1 R2

Chapter 8 - Part 1

Shift Microoperations
 From Table 7-5:  Let R2 = 11001001  Then after the operation, R1 becomes:
Symbolic Designation R1 n sl R2 R1 n sr R2
R1 10010010 01100100

Description Shift Left Shift Right

Operation R1 n sl R2 R1 n sr R2

 Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data shifted in, or to catch the data shifted out.  Other shifts are possible (rotates, arithmetic) (see Chapter 10).
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Control and Datapath

A module is composed of a control and a datapath.  Control part is mainly a sequential circuit which outputs control signals to datapath.  Control signals are timing signals which sequence the operations in the datapath  The datapath is composed of registers adders, shifters and logic used to select registers and move data between registers.
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Control and Datapath

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Algorithmic State Machines (ASM)

 The control sequence and datapath tasks are specified by an algorithm.  The most important part of digital design is the formulation of algorithms for achieving desired objectives.  The algorithms will be implemented in hardware as an integrated circuit.  A flowchart to define hardware algorithms is called an Algorithmic State Machine (ASM) chart.
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Algorithmic State Machines (ASM)

 The ASM chart is composed of three basic elements:
The state box The decision box The conditional box

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ASM State Box

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ASM Condition Box

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ASM with Conditional Outputs

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Algorithmic State Machines (ASM)

 An ASM block is a structure consisting of a state box and all decision and conditional boxes connected to its exit path.

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ASM Example
 A datapath consist of two JK flip-flops E and F and a four bit binary counter A[3:0].  A Start signal clears the counter A and flip-flop F.  At each following clock pulse counter is incremented.  If counter bit A[2]=0 E is cleared to 0 and count continues.  If A[2]= 1 E is set to 1, If A[3]=0 count continues else if A[3]=1 the F is set to 1 with next clock pulse and system stops.  If Start=0 the system remains in its initial state. If Start=1 operation starts again.
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ASM Example

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ASM Example

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ASM Example

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State Diagram of Controller

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State Table of Controller

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Flip-flop input equations of the controller

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Logic diagram of the controller

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Example
 Design a sequence detector that searches for a series of binary inputs to satisfy the pattern 01[0*]1, where [0*] is any umber of consecutive zeroes.  The output (Z) should become true every time the sequence is found.

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Example

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Example
 Design a system with three registers A,B,R to perform following operations:
When START is 1 load A and B registers with external data (IN1 and IN2) with the positive edge of the clock. Calculate A*B by repeated addition of contents of A register to R register. When multiplication is done wait for another START signal to load registers with new data.

 Design the system using an ASM chart.

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Summary
 Register Transfer Level(RTL)  Algorithmic State Machines (ASM)

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