Chp2introductiontothe68000microprocessor Copy 110627223604 Phpapp01

Introduction to The 68k QP
68k Instruction Set
Size
Destination Source
MOVE.B
Opcode
D0, D1
Operand
Assembly Language Progamming

Machine Instruction
0011 0000 0000 0011
0011 Op-code
000000 First operand
000111 Second operand
Types of instruction i.e. addition or subtraction Data size, byte, word or long word The amount of the word in complete instruction Where the data for an instruction (operand) can find
Cycle of Instruction
Collection
Implement
Cycle of Instruction
Collection phase:
cont
Fill-in program counter with instruction address Collect instruction from memory, put in the instruction register For control the instruction, clean-up PC for next instruction
Implement phase:
Count for the operation address Collect operation Do the operation Store the product of operation Back to first step
68K Addressing Modes

Addressing Modes
Register Direct Addressing Data Register Direct Address Register Direct Absolute Data Addressing Absolute Short Absolute Long Program Counter Relative Addressing Relative with offset Relative with Index Offset Register Indirect Addressing Register Indirect Postincrement Register Indirect Predecrement Register Indirect Register Indirect with Offset Indexed Register Indirect with offset Immediate Data addressing Immediate Quick Immediate Implied Addressing Implied Register
Syntax
Dn An xxx.W xxx.L d16 (PC) d8 (PC,Xn) (An) (An)+ -(An) d16(An) d8 (An, Xn) #xxx #1-#8 SR USP SP PC
Register Direct Addressing

Data Register Direct MOVE.B D0,D3

Cont
Data Register Direct MOVE.W D0,D3

Cont
Data Register Direct MOVE.L D0,D3

Cont
Address Register Direct MOVEA.L A3,A0

Cont
Address Register Direct MOVEA A3,A0
Absolute Data Addressing

Absolute Long Mode CLR.B $10000
010000 42 010002 55
51 13
010000 010002
00 55
51 13

Cont
Absolute Long Mode CLR.W $10000
010000 42 010002 55
51 13
010000 010002
00 55
00 13

Cont
Absolute Long Mode CLR.L $10000
010000 42 010002 55
51 13
010000 010002
00 00
00 00

Cont
Absolute Short Mode CLR.B $1000
01000 42 01002 55
51 13
01000 00 01002 55
51 13
Absolute Short vs Absolute Long

Absolute short:

Cont
16-bit (0000~7FFF, 8000~FFFF) Sign extend the 16-bit value into 24-bit (000000~007FFF, FF8000~FFFFFF)
Absolute Long:

24-bit(000000~FFFFFF) No sign extension
PC Relative Addressing
PC Relative with Offset MOVE.W $1200(PC), D5
Assume the instruction is located at $122000 Effective address: $00122002 + $00001200 = $00123202
Cont
PC Relative with Offset
Cont
PC Relative with Index and Offset MOVE.L -20(PC,A2.L),D5

Assume the instruction is located at $00010200
Effective address: $00010202 + $00020030 + $FFFFFFEC = $0003021E
Cont
PC Relative with Index and Offset
Register Indirect Addressing

MOVE.L D0,(A0)
Address Register Indirect Addressing Post-Increment PostMOVE.W (A5)+,D0
Address Register Indirect Addressing Predecrement

MOVE.W D0,-(A6)
Address Register Indirect Addressing With Offset

MOVE.W 6(A0),D0
Address Register Indirect Addressing with Index & Offset

MOVE.W $10(A0,D0.L), A1
Immediate Addressing
Immediate MOVE.L #$1FFFF, D0 Before:D0 = 12345678 After: D0 = 0001FFFF
Note: $ = value for hexadecimal @ = value for octal % = value for binary & or blank = decimal AB = character ASCII
Immediate Addressing
Cont
Quick Immediate 1. MOVEQ #$2C, D3 Before: D3 = 1234562C After: D3 = 0000002C 2. MOVEQ #$8F, D3 Before: D3 = 1234568F After: D3 = FFFFFF8F
Implied Addressing

ANDI #$27, SR MOVE CCR, CODES TRAPV
68K Instruction Set

Data transfer Arithmetic Logical Shift and rotate Bit manipulation BCD operations Program control System control
68K Instruction Set

Cont
Data Transfer Instructions
68K Instruction Set

Cont
Integer Arithmetic Instructions
68K Instruction Set

Cont
Compare and Test Instructions
68K Instruction Set

Cont
Logic Instructions
68K Instruction Set

Cont
Shift Instructions
68K Instruction Set

Cont
Rotate Instructions
68K Instruction Set

Cont
Bit-Manipulation Instructions
68K Instruction Set

Cont
Subroutine Control Instructions
68K Instruction Set

Cont
Binary-Coded Decimal Arithmetic Instructions
Data Transfer Instruction

Take Data from Memory Operation Load
MOVE.W
D1
$10000, D1
D1 FE ED 42 51
FE ED BE EF
010000 010002
42 55
51 13
010000 42 010002 55
51 13

Cont
MOVE.L
D1
$1000, D1
D1 42 51 55 13
FE ED BE EF
01000 42 01002 55
51 13
01000 42 01002 55
51 13

Cont
MOVE.B
D1
$1000, D1
D1 FE ED BE 42
FE ED BE EF
01000 42 01002 55
51 13
01000 42 01002 55
51 13

Cont
Store Data into Memory Operation Save
MOVE.W
D1
D1, $1000
D1 FE ED BE EF
FE ED BE EF
01000 42 01002 55
51 13
01000 BE EF 01002 55 13

Cont
MOVE.L
D1
D1, $1000
D1 FE ED BE EF
FE ED BE EF
01000 42 01002 55
51 13
01000 FE ED 01002 BE EF

Cont
MOVE.B
D1
D1, $1000
D1 FE ED BE EF
FE ED BE EF
01000 42 01002 55
51 13
01000 EF 51 01002 55 13

Cont
Moving Memory Data To Memory
MOVE.W
$1000, $1006
001000 001002 001004 001006
42 55 01 90
51 13 02 AB
001000 001002 001004 001006
42 55 01 42
51 13 02 51

Cont
Moving Memory Data To Memory
MOVE.B
$1000, $1006
001000 001002 001004 001006
42 55 01 90
51 13 02 AB
001000 001002 001004 001006
42 55 01 42
51 13 02 AB

Cont
Immediate Mode
MOVE.B
D1
#$F1, D1
D1 FE ED BE F1
FE ED BE EF
MOVE.B D1, #$F1

Cont
MOVEQ Instruction
MOVEQ
D1
#$F1, D1
D1 FF FF FF F1
FE ED BE EF

Cont
Fill up Memory
MOVE.B
001000 001002 001004 001006
#$F1, $1000
42 55 01 90 51 13 02 AB 001000 001002 001004 001006 F1 55 01 90 51 13 02 AB

Cont
EXG Instruction
EXG
D1, D5
D1 12 12 20 30 D5 00 FF 48 7C
D1 00 FF 48 7C D5 12 12 20 30

Cont
SWAP Instruction
SWAP
D1
D1 12 34 20 30
D1 20 30 12 34

Cont
LEA Instruction Load Effective Address
LEA
$00200001, A0
A0 00 20 00 01
A0 00 12 70 02
Similar to: MOVEA.L #00200001, A0

Cont
LEA
(A1), A0
A0 00 10 FF FF A1 00 10 FF FF
A0 00 12 70 02 A1 00 10 FF FF
Similar to: MOVEA.L A1, A0

Cont
LEA
8(A0), A1
A0 00 12 70 02 A1 00 12 70 0A
A0 00 12 70 02 A1 00 00 40 00

Cont
LEA
8(A0, D4.L), A1
D4 00 00 20 00 A0 00 12 70 02 A1 00 12 90 0A
D4 00 00 20 00 A0 00 12 70 02 A1 00 00 40 00
Arithmetic Instruction
ADD Instruction Destination + Source p Destination ADD.W D1, D3
D1 12 34 56 78 D1 12 34 56 78 D3 FD CC 57 9B
$1000,$2000 $2000,D3
D3 FD CC 01 23
ADD.W ADD.W
Cont
Data Addition in Memory

Problem:
A = B + C, where A, B & C are memory
Solution:
- Copy the first word (B) from memory to register - Add the second word (C) to register - Copy the addition product to the memory
Program:
MOVE.W ADD.W MOVE.W B,D1 C,D1 D1,A ; Take B ; Add with C ; Store product in A
Cont
Carry Production (0~255) Unsigned integers ADD.B D0, D3
No carry, C = 0
9-bit after addition, C = 1
Cont
Overflow Production (-128~+127) signed integers
Cont
ADD.B D0, D3
V = 0, C = 0
V = 1, C = 0
V = 0, C = 1
V = 1, C = 1
Cont
ADDA Instruction
Data size: W, L ADDA.L #$70, A1 A1 00 00 20 30 A1 00 00 20 A0
Use ADDQ.L #$1, A1 for value 1~8, it is faster than ADDA.L #$1, A1
Cont
SUBA Instruction
Data size: W, L
SUBA.L
#$70,A1
A1 00 00 1F C0
A1 00 00 20 30
Use SUBQ.L #$1, A1 for value 1~8, it is faster than SUBA.L #$1, A1
Cont
ADDQ Instruction ADDQ.W #3,D6

1~8 only
D6 12 34 56 FF
D6 12 34 57 02
Cont
ADDQ
vs
MOVEQ
ADDQ MOVEQ -128+127 Dn only L only
Source Data Size
1..8 B, W, L
Destination Any
Cont
SUB Instruction Destination - Source p Destination SUB.B D3, D1

D1 12 34 56 78 D1 12 34 56 55 D3 FD CC 01 23
D3 FD CC 01 23
SUB.W
$1000, $2000
Cont
The Effect for V Flag after ADD/SUB
ADD
s
S, D
d Answer (d)
Any Any Positive Negative Negative Positive
Overflow
Nothing happen (always V=0) Nothing happen (always V=0) V=0 V=1 V=0 V=1
Positive Negative Negative Positive Positive Positive
Negative Negative
Cont
The Effect for V Flag after ADD/SUB
SUB s
Positive
S, D d
Positive
Answer (d)
Any Any Positive Negative Negative Positive
Overflow
Nothing happen (always V=0) Nothing happen (always V=0) V=0 V=1 V=0 V=1
Negative Negative Negative Positive Positive Negative
Cont
The Effect for Flag after SUB

C = Set; 2 unsigned values V = Set; 2 signed values Z = Set; product is 0 N = MSB X=C
Cont
The Effect for Flag after SUB

SUB.W D1,D0 ;D0 D0 D1
D1 before SUB
D0 00 D0 00 D0 00 D0 00 D0 00 D0 00 00 00 00 00 00 00 30 00 AA FD 20 E0 3E 00 55 00 00 00
D0 before SUB
D0 00 D0 00 D0 00 D0 00 D0 00 D0 00 00 00 00 00 00 00 30 00 FF 00 90 70 40 40 FF 00 00 00
D1 before SUB
D1 00 D1 00 D1 00 D1 00 D1 00 D1 00 00 00 00 00 00 00 00 00 55 03 70 90 02 40 AA 00 00 00
XNZVC
After instruction
0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1
Cont
SUBQ Instruction SUBQ.W #7,D6

1~8 only
D6 12 34 56 FF
D6 12 34 56 F8
Cont
SUBQ
vs
MOVEQ
SUBQ MOVEQ -128+127 Dn only L only
Source Data Size
1..8 B, W, L
Destination Any
Cont
Multiplication Instruction 1. Unsigned number MULU.W source, Dn 2. Signed number MULS.W source, Dn
Note:
Source: 16-bit of any address mode Both operand: 32-bit data register Multiply product: 32-bit stores in destination data register
Cont
MULU 1. Multiply 256 with 2 MOVE.W #256, D3 MULU.W #2, D3

D3 FD CC 01 00
16-bit
D3 00 00 02 00
32-bit
Cont
MULU 2. Multiply #$FFFF with #$FFFF MULU.W #$FFFF, D3

D3 FD CC FF FF Note:
FFFF = 65535 65535 * 65535 = 4294836225 = FFFE0001
D3 FF FE 00 01
Cont
MULS Multiply #$FFFF with #$FFFF MULS.W #-1, D3

D3 FD CC FF FF Note:
D3 = -1 (-1) * (-1) = 1
D3 00 00 00 01
Cont
MULS & MULU

Content in hex As unsigned decimal As signed decimal Location XX Location YY Register D0 Register D1 0003 B000 00A0 FF00 3 45056 160 65280 3 -20480 160 -256
MULS MULU MULS MULU MULS MULU
XX, D0 XX, D0 XX, D1 XX, D1 YY, D1 YY, D1
D0=000001E0 D0=000001E0 D1=FFFFFD00 D1=0002FD00 D1=00500000 D1=AF500000
(3 x 160 = 48010) (3 x 160 = 48010) (3 x (-256) = -76810) (3x 65280 = 19584010) (-20480 x (-256) = 524288010) (45056 x 65280 = 294125568010)
Cont
Division Instruction
1. Unsigned number DIVU.W source, Dn 2. Signed number DIVS.W source, Dn
Note:
Source: 16-bit of any address mode Both operand: 32-bit data register Division product: lower word destination register Remainder: upper word destination register
Cont
Division Instruction Example 1: DIVU.W D0, D3

D0 FE CC 01 00 D3 00 10 00 01 D0 FE CC 01 00 D5 00 01 10 00
Remainder Quotient
Cont
Division Instruction Example 2: (Overflow) MOVE.L #$40000, D3 DIVU.W #2, D3

Result D3 = 100 0000 0000 0000 0000 (19-bit) Destination can hold 16-bit data only Operand remains unchanged and a division overflow sets the V = 1
Cont
Division Instruction Example 3: (Case divide with zero) MOVE.L #$122, D3 CLR D0 DIV D0, D3
Cont
Division Instruction Example 3: (Case divide with zero)

Location XX Location YY Location ZZ Register D0 Register D1 Content in hex 0012 FFAE FF00 00000308 FFFFFE00 Decimal Decimal 18 Decimal 82 Unsigned decimal 65280 Decimal 776 Decimal -512
Cont
Division Instruction Example 3: (Case divide with zero)

Instruction DIVU XX,D0 DIVS XX,D1 DIVS YY,D0 DIVS YY,D1 DIVU ZZ,D0 DIVU ZZ,D1 Result in hex D0=0002002B D1=FFF8FFE4 0026FFF7 FFEC0006 03080000 FFFFFE00 Quotient Decimal 43 Decimal -28 -9 6 0 65792 Remainder Decimal 2 Decimal 8 38 -20 308 65024
Cont
NEG Instruction (Negate) Form 2s complement X n 0 - X NEG.W D5

D5 34 67 00 F0 D5 34 67 FF 10
Cont
EXT Instruction (Sign Extend)

Convert byte @ word operand to word @ longword by extending the sign bit of the operand
EXT.W
D5
D5 34 67 00 F0 D5 34 27 20 65
D5 34 67 FF F0 D5 34 27 00 65
Cont
EXT Instruction (Sign Extend)

EXT.L
D5
D5 34 67 30 F0 D5 34 27 99 65
D5 00 00 30 F0 D5 FF FF 99 65
Practical Example
Write a sequence of program to compute X = 5 * Y + Z/W where Y, Z and W are 16-bit signed integers and the result is stored as longword X. Solution:
MOVE.W MULS MOVE.W EXT.L DIVS EXT.L ADD.L MOVE.L Y, D0 #5, D0 Z, D1 D1 W, D1 D1 D1, D0 D0, X Location and register Location X Location Y Location Z Register D0 Register D1 As Hexadecimal 0012 FFAE FF00 00000308 FFFFFE00
Compare & Test Instruction

Compare Instruction CMP CMP.W D1, D0
D0-D1 D0 D0 D0 D0 D0 D0 D0 D0 01 01 01 01 01 01 01 01 20 20 20 20 20 20 20 20 30 30 30 00 FF 10 70 90 40 41 40 00 FF 00 00 00 D1 D1 D1 D1 D1 D1 D1 D1 01 01 01 01 01 01 01 01 20 20 20 20 20 20 20 20 30 30 30 FF 00 20 90 70 40 40 41 FF 00 00 00 00 0000 0001 FFFF 0001 FFFF F000 E000 2000 X N Z V C 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 0 1 0
Logical Instruction
A 0 0 1 1
B 0 1 0 1
AB 0 0 0 1
AB 0 1 1 1
AB 0 1 1 0
A 1 1 0 0
B 1 0 1 0
Logical Instruction
Cont
AND.s ANDI.s OR.s ORI.s EOR.s EORI.s NOT.s
<sea>, <dea> #data, <dea> <sea>, <dea> #data, <dea> <sea>, <dea> #data, <dea> <ea>
Either one is Dn operand The 1st immediate operand Either one is Dn operand The 1st immediate operand Either one is Dn operand The 1st immediate operand
Logical Instruction
Cont
AND Instruction

To clear more than 1 bit in operand ADNI.L #$0F, D0 If D0 = $0000B2DA

D0 0000 0000 0000 0000 1011 0010 1101 1010 $0F 0000 0000 0000 0000 0000 0000 0000 1111 AB 0000 0000 0000 0000 0000 0000 0000 1010
@ D0 = $0000000A
Logical Instruction
Cont
OR Instruction

To set more than 1 bit in operand ORI.W #$00E0, D0 If D0 = $A22D

D0 1010 $E0 0000 AB 1010 0010 0000 0010 0010 1110 1110 1101 0000 1101
@ D0 = $A2ED
Logical Instruction
Cont
EOR Instruction

To invert more than 1 bit in operand EORI.W #$00FF, D0 If D0 = $A22D

D0 1010 $FF 0000 AB 1010 0010 0000 0010 0010 1111 1101 1101 1111 0010
@ D0 = $A2D2
Logical Instruction
Cont
NOT Instruction

To get 1s complement of the operand NOT.B D0 If D0 = $A22D

D0.B 0000 D0.B 1010 0000 0010 1111 1111 1101 0010
@ D0 = $A2D2
Shift Instruction
4 instructions of shift operations: ASL (arithmetic shift left) ASR (arithmetic shift right) LSL (logical shift left) LSR (logical shift right) Size: B, W, L Affected flag: X & C = depend to the bit shift out N & Z = depend to the product V = 1 if sign operand changes by shifting, but 0 for rotate
Shift Instruction
Cont
Arithmetic Shift Instruction
Example: ASR.B #2, D1 D1 12 34 56 F0

(-16)
D1 12 34 56 FC
(-4)
Shift Instruction
Cont
Logical Shift Instruction

Unsigned value
0
Example: LSR.B #2, D1
D1 12 34 56 F0
(240)
D1 12 34 56 3C
(60)
Rotate Instruction
4 instructions of rotate operations: ROL (rotate left) ROR (rotate right) ROXL (rotate left through X flag) ROXR (rotate right through X flag) Size: B, W, L Affected flag: X & C = depend to the bit shift out N & Z = depend to the product V = 1 if sign operand changes by shifting, but 0 for rotate
Rotate Instruction
Cont
Example: ROR.B D1 12 34 56 A1
(10100001)
#2, D1 D1 12 34 56 68
(01101000)
Rotate Instruction
Cont
Rotate Instruction through X
Example: ROXR.B #2, D1 D1 12 34 56 A1

(10100001)
D1 12 34 56 A8
(10101000)
Example
Running light in address $80000
MOVE.B REPEAT MOVE.B JSR ROL.B BRA #1,D0 D0,$800000 DELAY #1,D0 REPEAT
;Delay
Bit Manipulation Instruction

Test the specified bit in the destination Data size = B or only 1. The bit manipulation instruction included:
a. BCHG (bit test and change) instruction b. BCLR (bit test and clear) instruction c. BSET (bit test and set) instruction d. BTST (bit test) instruction

Cont
Example 1:
In address $FF8000 contains $AA. What is the result after BTST.B #3, $FF8000?
Solution:

($FF8000) = 101010102 where the 3rd bit is 1. Therefore Z = 0

Cont
Example 2:
Data register D5 contains 2C3459A7. What is the state of the Z flag and what are the contents of D5 after BCHG #6, D5?
Solution:

lower byte of D5 = 101001112. Bit 6, 1<0>100111, is a 0. This will set the Z flag & complement bit 6. This result in D5 = 2C3459E716.

Cont
Example 3:
Data registers D6 and D7 contain 0000000C and 75793290, respectively. What is the result of BCLR D6, D7?
Solution:

Register D6 specifies that the 12th bit position 001<1>001010010000) should be tested and cleared. Since the 12th bit is a 1, Z = 0 bit 12 of D7 will be cleared D7 = 75792290.

Cont
Example 4:
What is the result of BSET #2,(A3)?
Solution:
The bit in position 2 of the memory location pointed to by A3 is tested and then set.
Subroutine Control Instruction

Flow Chart Symbol

Program Control Structure
Cont
Cont
Jump Instruction JMP Unconditional transfer to target destination PC n effective address JMP <ea> Type of effective address:
a. Absolute short b. Absolute long c. Address register indirect

Jump Instruction JMP
JMP START ; START = $1000
0100 1110 1111 1000 0001 0000 0000 0000
Cont
JMP
$FF8000
0100 1110 1111 1001 0000 0000 1111 1111 1000 0000 0000 0000

Bcc (branch condition) Instruction
Bcc<ea>
Instruction BEQ BNE BMI BPL BCS/LO BCC/HS BVS BVC BGT BLT BGE BLE BHI BLS Meaning EQual to zero Not Equal to zero Minus Plus Carry Set/LOwer Carry Clear/Higher or Same oVerflow Set oVerflow Clear GreaTer than Less Than Greater than or Equal Less than or Equal Higher Lower than or Same Arithmetic U U U U U U S S S S S S U U
Cont
If the test is true Z=1 Z=0 N=1 N=0 C=1 C=0 V=1 V=0 Z+(NV)=0 NV=1 NV=0 Z+(NV)=0 C+Z=0 C+Z=1

Branch Always Instruction - BRA
PC n PC + offset BRA.s <ea> Short branch: -128 e PC e +127 Syntax: BRA.S Long branch: -32k e PC e 32k Syntax: BRA.L
Cont

Control Constructions
1. IF condition THEN action 1; 2. IF condition THEN action 1 ELSE action 2; 3. FOR counter = initial TO final value DO action 1; 4. REPEAT action1 UNTIL condition;
Cont
5. WHILE condition DO action 1; 6. CASE selector OF action 1, action 2, . . action N;

Example for IF - THEN
IF A=10 THEN Action 1 CMPI.W #10, VARA BNE NEXT . . Action 1 . NEXT
Cont
F T

Example for IF THEN ELSE
IF A<=0 THEN Action 1; ELSE Action 2 TST.W BLE
. .
Cont
VARA NEXT1
Action 1
BRA NEXT1
. .
NEXT
Action 2
NEXT

Example for FOR LOOP
FOR I=1 TO 10 DO Action 1 MOVE.W #9, D7 LOOP
. . . Action 1
Cont
DBF
D7, LOOP

Example for REPEAT UNTIL
REPEAT Action 1 UNTIL A=0 or maximum count is reached MOVE.W SUBQ.W LOOP . . Action 1 . TST.W VARA DBNE D7, LOOP LIMIT,D7 #1, D7
Cont

Example for WHILE DO
WHILE A<=10 and maximum count is not reached DO Action 1 MOVE.W CMPI.W DBGT LIMIT, D7 #10, VARA D7, LOOP
Cont
AGAIN LOOP
. . Action 1 . BRA AGAIN NEXT . . .
Action 2
BCD (Binary Coded Decimal) Instruction

Each BCD byte contents 2 digit of 4-bit BCD. Each BCD instruction involve in X bit. Z bit is changed if the product is not zero. Before doing the first BCD operation, it have to start with X=0 and Z=1. Syntax: ABCD Dx,Dy (source)10 + (destination)10 + X p destination ABCD- (Ay)-(Ax) NBCD <ea> 0 (source)10 X p destination SBCD Dx,Dy (destination)10 - (source)10 - X p destination

ABCD and SBCD Instructions
Example 1:
Add BCD number in D0 to D1. MOVE #4, CCR ; x=0 and z=1 ABCD D0, D1
Cont
Example 2:
Subtract BCD number in D0 from D1 MOVE #4, CCR ; x=0 and z=1 SBCD D0, D1

BCD Instruction
Addition for 2 BCD number 8 bit (byte). MOVE #4,CCR ;x=0 and z=1 ABCD -(A0),-(A1) ABCD -(A0),-(A1) ABCD -(A0),-(A1) ABCD -(A0),-(A1)
A1 after addition p Upper Byte Lower Middle A1 before addition p
Cont
Upper Middle Lower Byte
Destination
A0 after addition
Upper Byte Lower Middle
Upper Middle Lower Byte
Source
A0 before addition

NBCD Instruction

Cont
Use 9s @ 10s complement notation to represent a negative BCD number
Example 1:
What is the 10s complement for fill-in D0. Let say D0 = 23.
MOVE #0,CCR NBCD D0 NBCD operation: Original D0: X bit: Product:
100 -23 - 0 77
(0 borrow 1)

NBCD Instruction
Example 2:
What is the 9s complement for fill-in D0. Let say D0 = 23. MOVE #$10,CCR NBCD D0 NBCD operation : 100 (0 borrow 1) Original D0 : -23 X bit: - 1 Product : 76
Cont
Stack and Subroutine

Stack

Data structure that is used to save and restore information in a last-in, first-out (LIFO) fashion. Register A7 is implicitly used as the stack pointer. Push (save): MOVE source, -(SP) or MOVE.L source, -(SP) Pop (retrieve): MOVE (SP)+, destination or MOVE.L (SP)+, destination

Cont
Stack

Cont
Stack
STACKA DS.W MOVEA.L MOVE.L MOVE.W MOVE.W MOVE.L MOVE.L 50 #STACKA + 100, A2 D1, -(A2) VAR, -(A2) #$25, -(A2) (A2)+, D2 (A2)+, D3

Cont
Stack
Subroutine
Subroutine
Cont
Subroutine Concept A program structure where one part of the program is called the main program. In addition to this, a smaller segment attached to the main program, known as a subroutine. The subroutine is written to provide a function that must be performed at various points in the main program. A return instruction must be included at the end of the subroutine to initiate the return sequence to the main program environment. The instructions provided to transfer control from the main program to a subroutine and return control back to the main program are called subroutine-handling instructions.
Subroutine
Cont
Subroutine Control Instructions JSR, BSR, RTS & RTR
Interrupt

An external event which informs the CPU that a device needs its service. Interrupt Service Routine (ISR):
a. a program which associates with interrupt. b. also called the interrupt handler c. there are 4 bytes of memory allocated as interrupt vector table. d. handled in the supervisor mode, S = 1.
Interrupt
Cont
Example 1:
Calculate the sum of 10 numbers in the address memory $2000.
extra

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Introduction to The 68k QP

68k Instruction Set

Assembly Language Progamming

000000 First operand

000111 Second operand

68K Addressing Modes

Register Direct Addressing

Register Direct Addressing

Data Register Direct MOVE.W D0,D3

Register Direct Addressing

Data Register Direct MOVE.L D0,D3

Register Direct Addressing

Address Register Direct MOVEA.L A3,A0

Register Direct Addressing

Address Register Direct MOVEA A3,A0

Absolute Data Addressing

Absolute Data Addressing

Absolute Long Mode CLR.W $10000

Absolute Data Addressing

Absolute Long Mode CLR.L $10000

Absolute Data Addressing

Absolute Short Mode CLR.B $1000

Absolute Short vs Absolute Long

24-bit(000000~FFFFFF) No sign extension

PC Relative with Offset

PC Relative with Index and Offset MOVE.L -20(PC,A2.L),D5

Effective address: $00010202 + $00020030 + $FFFFFFEC = $0003021E

PC Relative with Index and Offset

Register Indirect Addressing

Address Register Indirect Addressing Post-Increment PostMOVE.W (A5)+,D0

Address Register Indirect Addressing Predecrement

Address Register Indirect Addressing With Offset

Address Register Indirect Addressing with Index & Offset

ANDI #$27, SR MOVE CCR, CODES TRAPV

68K Instruction Set

68K Instruction Set

Data Transfer Instructions

68K Instruction Set

Integer Arithmetic Instructions

68K Instruction Set

Compare and Test Instructions

68K Instruction Set

68K Instruction Set

68K Instruction Set

68K Instruction Set

68K Instruction Set

Subroutine Control Instructions

68K Instruction Set

Binary-Coded Decimal Arithmetic Instructions

Data Transfer Instruction

Data Transfer Instruction

Take Data from Memory Operation Load

Data Transfer Instruction

Take Data from Memory Operation Load

Data Transfer Instruction

Store Data into Memory Operation Save

Data Transfer Instruction

Store Data into Memory Operation Save

Data Transfer Instruction

Store Data into Memory Operation Save

Data Transfer Instruction

Moving Memory Data To Memory

001000 001002 001004 001006

NEG Instruction (Negate) Form 2s complement X n 0 - X NEG.W D5