Outline

y Multiplication y Sequential Architectures y Parallel Architectures

y y

Partial Product Generation Partial Product Accumulation

y Wallace Strategy y Dadda Strategy y Modified Wallace Strategy y Comparisons

Multiplication
y Compute P = X Y

where y X: xn-1 x1x0 y Y: yn-1 y1y0 y P: p2n-1 p1p0

X is an N-bit unsigned number Y is an N-bit unsigned number P is a 2N-bit unsigned number xn-1 x1x0 yn-1 y1y0 p2n-1 pn-1 p1p0
3

Sequential Multiplier

Parallel Multiplier

Parallel Multiplier (Dot Notation)

Wallace Reduction Strategy [1]

y In each column of partial products, every three adjacent

rows construct a group. These groups should be nonoverlapped.

y Then reduction in each group is done by one of the

following cases:
y Applying a full adder to the 3-bit groups y Applying a half adder to the 2-bit groups and y Passing any 1-bit group to the next stage without change

Wallace Reduction Strategy (ctn.)

Wallace Reduction Strategy (ctn.)

Dadda Reduction Strategy [2]

y This method does as few reductions as possible. y To determine how much reduction is required, the

maximum height of each stage is calculated by working back from the final stage (i.e., 2 rows).
y 2, 3, 4, 6, 9, 13, 19, 28, 42, 63, etc. y In our example, the first stage contains 9 rows; therefore,

we would have 4 reduction stages as (9, 6, 4, 3, 2)

10

Dadda Reduction Strategy (cnt.)

9, 6, 4, 3, 2

9, 6, 4, 3, 2

11

Dadda Reduction Strategy (cnt.)

2, 3, 4, 6, 9

2, 3, 4, 6, 9 2, 3, 4, 6, 9 2, 3, 4, 6, 9

12

Modified Wallace Reduction Strategy [3]

y This reduction method uses full adders as in the

conventional Wallace reduction.

y Using half adders is somehow similar to the Dadda s

method.
y In essence, half adders are used only when it is

necessary for not exceeding the number of stages.

13

Modified Wallace Reduction Strategy (ctn.)

9, 6, 4, 3, 2

9, 6, 4, 3, 2

14

Modified Wallace Reduction Strategy (ctn.)

2, 3, 4, 6, 9

2, 3, 4, 6, 9 2, 3, 4, 6, 9

15

Comparison [3]

16

References
y [1] Wallace, C. S., A Suggestion for a Fast Multiplier,

IEEE Transactions on Computers, Vol. EC-13, No. 1, pp. 14-17, 1964.

y [2] Waters, R. S. and E. E. Swartzlander Jr., A Reduced

Complexity Wallace Multiplier Reduction, IEEE Transactions on Computers, Vol. 59, No. 8, pp. 11341137, 2010.
y [3] Dadda, L., Some Schemes for Parallel Multipliers,

Alta Frequenza, Vol. 34, pp. 349-356, 1965.

17

Thanks for your attention

18