Complementary MOS fabrication

CMOS Technology has both N-Type and P-Type MOSFETs on the same chip.

VDD A Y

GND

A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1

The two main technologies to do this task are: P-Well Substrate N-type P-type well inside the N-type wafer where N-channel MOSFET is built N-channel MOSFET is built directly inside the substrate N-Well Substrate P-type N-type well inside the P-type wafer where P-channel MOSFET is built P-channel MOSFET is built directly inside the substrate To improve the device performance and density two advanced technologies for CMOS fabrication are Twin Tub Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate. Silicon-on-Insulator (SOI) CMOS Process SOI allows isolated nMOS and pMOS transistors side-by-side on an insulating substrate Advantages : prevents latch up, increases integration density, reduces parasitic capacitance

N well process
Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps Adv:-lesser effect of substrate bias on Threshold voltage and lesser parasitic capacitances. Also the process steps are similar to conventional N-channel MOS fabrication.
A GND Y VDD

p+

n+

n+ p substrate

p+ n well

p+

n+

substrate tap

well tap

Cross-section taken along dashed line

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

 Six masks
n-well Polysilicon n+ diffusion p+ diffusion Contact Metal
n well

Polysilicon

n+ Diffusion

p+ Diffusion

Contact

Metal

Processing steps
Start with blank wafer

p substrate

First step will be to form the n-well For that first deposit SiO2 and pattern it using lithography
SiO2

p substrate

Spin Photo resist

Photoresist SiO2

p substrate

Expose photoresist through n-well mask Strip off exposed photoresist

Photoresist SiO2

p substrate

Etch oxide with hydrofluoric acid (HF)

Photoresist SiO2

p substrate

Strip off remaining photoresist

SiO2

p substrate

n-well is formed with diffusion or ion implantation

SiO2 n well

Strip off the remaining oxide using HF

n well p substrate

Deposit very thin layer of gate oxide and a thin layer of polysilicon Heavily doped to be good conductor
Polysilicon Thin gate oxide n well p substrate

Polysilicon Patterning

Polysilicon

Polysilicon Thin gate oxide n well p substrate

Deposit oxide and pattern to expose where n+ dopants should be diffused or implanted to form n+ source and drain implants and substrate

n well p substrate

n well p substrate

n+ is diffused through the patterned oxide. This is a self-aligned process where gate blocks diffusion
n+ Diffusion

n well p substrate

After n+ diffusion
n+ n+ n well p substrate n+

Remove the oxide completely

n+

n+ n well p substrate

n+

Next step is to form p+ diffusion regions for pMOS source and drain and substrate contact

p+ Diffusion

p+

n+

n+ p substrate

p+ n well

p+

n+

To wire together the devices cover chip with thick field oxide and etch oxide where contact cuts are needed

Contact Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Deposit aluminium over the wafer and pattern to remove excess metal, leaving wires

Metal

Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Fabrication and Layout

Slide 13

 Latch up in CMOS

Latchup is defined as the generation of a low impedance path in CMOS chips between power supply rail and the ground rail due to interaction of parasitic pnp and npn bipolar transistors. This causes excessive current flows and potential permanent damage to the devices If some external disturbance occurs, causing the collector current of one of the parasitic transistors to increase, the resulting feedback loop causes the current perturbation to be multiplied by F1.F2 This event triggers the silicon-controlled rectifier and each transistor drives the other with positive feedback eventually creating and sustaining a low impedance path between power and the ground rails resulting in latch-up.

How to avoid latch up

Use p+ guardband rings connected to ground around nMOS transistors and n+ guard rings connected to VDD around pMOS transistors to reduce Rw and Rsub and to capture injected minority carriers before they reach the base of the parasitic BJT. Increase the substrate doping to minimise its resistance Provide isolation between the n type and ptype devices SOI technology

Twin tub process

Provide separate optimization of the n-type and p-type transistors Make it possible to optimize "Vt", "body effect", and the "gain" of n, p devices independently. Starting material: an n+ or p+ substrate with lightly doped - "epitaxial" or "epi" layer to protect "latch up Process sequence a. Tub formation b. Thin-Oxide construction c. Source & drain implantations d. Contact cut definition e. Metallization

Silicon-on-Insulator (SOI) CMOS Process

Partially Depleted : In this type of SOI MOSFET, the maximum depletion width is lesser than the thickness of SOI when the channel is inverted. Advantages: Easy to manufacture and easily understood Fully Depleted : In this type, the doping and the thickness of the SOI is varied such that the SOI is fully depleted when the channel is inverted. The maximum depletion width is greater than the thickness of the SOI Advantages:Leakage and power consumption drastically reduced. Easier to contain short channel effects

A thin film of very lightly doped semiconductor is grown over sapphire or SiO2

Anisotropic etching is done to form n islands

P type implant is done by masking the other n island with photoresist. p-island will form nchannel device

N type implant is done by masking the p island with photoresist. n-island will form p-channel device

Gate oxide is grown through thermal oxidation Next deposit Doped Polysilicon on top of this

Pattern and Etch the polysilicon

n-implantation for source & drain of p channel device

p-implantation for source & drain of n channel device

Grow phosphorus glass or Silicon dioxide over the entire surface Etch glass to form contact cut Evaporating alumnium over the surface and etch it for desired metal connections

Advantages : increases integration density, reduces parasitic capacitance, reduced leakage currents No body effect problems Enhanced radiation tolerance Disadvantages Manufacturing complexity Cost

Dielectric deposition
Dielectric films:- isolation and passivation of devices Commonly used deposition methods
APCVD-atmospheric pressure CVD LPCVD-Low pressure CVD PECVD-Plasma enhanced CVD
Plasma energy+thermal energy Considerations in selecting deposition process- substrate temperature, deposition rate, film uniformity etc

Si02 deposition
CVD oxides used to complement thermal oxide Si02 -insulate multilevel metallization -to mask ion implantation and diffusion -to increase the thickness of thermally grown field oxide. Reaction Low temp reaction SiH4(gas)+O2(gas) SiO2(solid)+2H2(gas) This reaction takes place at 450oC.It can be done by APCVD or LPCVD Moderate temp reaction Si(OC2H5)4 SiO2+ byproducts Usually done by LPCVD Done at 700oC

 High temperature reaction -SiCl2H2+ 2N2O SiO2+2N2+2HCl -Done at 900oC Deposition temperature increases purity increases At high temperature composition of oxide is similar to thermally grown SiO2 Step coverage
Surface topology of a deposited film to various steps on the semiconductor substrate Conformal step coverage due to rapid migration of reactants after adsorption on the step surface

Conformal step coverage

Non Conformal step coverage

Non conformal step- reactants adsorb and react without significant migration High temperature-good conformal coverage

Silicon nitride (Si3N4)

Used to passivate devices-barrier to diffusion of water and Na Selective oxidation-nitrides oxidises slowly-prevents underlying silicon from oxidising Low deposition temp deposited over fabricated devices and serve as final passivation . Difficult to grow thermal nitride-Slow growth rate & high growth temperature Deposited at intermediate temperature LPCVD or low temp Plasma assisted CVD SiCl2H2+4NH2 Si3N4+6HCl+6H2 Good film uniformity and high wafer throughput PECVD 3SiH4(gas)+4NH3(gas) Si3N4(solid)+12H2(gas)

Low k dielectric materials

Multilevel metallization-minimise time delay due to parasitic resistance R and Capacitance C Interconnect materials with low resistivity and interlayer films with low capacitance C=EA/d To reduce the capacitance low k materials are used where E=E0k Eg:-Fluorinated hydrocarbon,Fluorosilicate glass

High k dielectric materials

Storage Capacitance in DRAM needs to a high value A minimum d is determined for maximum allowed leakage current and minimum required braekdown voltage Area can be increased by usingstacked or trench structures For planar structure area is reduced by increasing the DRAM density. So go for High k materials Eg:-Ta2O5,TiO2etc

Poly silicon deposition

For aluminium the time to breakdown decreases as the thickness decreases.But for polysilicon it remains almost constant. As device dimensions shrink the gate oxide becomes very thin .So aluminium not preferred. This happens because of the migration of Aluminium atoms through the gate oxide at high electric fields Also polysilicon can withstand high temp compared to aluminium. It is used as the gate material for MOSFETs It is also used for fabrication of resistors It adheres well to SiO2 SiH4 Si+2H2. This reaction takes place at about 600oC