8051 Microcontroller

Assembly Language

8051
This is an 8 bit microcontroller originally developed by Intel in 1980 It is the world's most popular microcontroller core, made by many independent manufacturers (truly multisourced) There were 126 million 8051s (and variants) shipped in 1993!!
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8051 Summary
A typical 8051 contains: CPU with Boolean processor 5 or 6 interrupts: 2 are external 2 priority levels 2 or 3 16-bit timer/counters programmable full-duplex serial port (baud rate provided by one of the timers) 32 I/O lines (four 8-bit ports) RAM - ROM/EPROM in some models
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Why assembly language?

Reduced code size Lower program execution time For specific application-motor control Cheaper Better under standing of the controller

Topics covered in this session

Memory Organization Registers ACC,DPTR,SP,PSW Addressing Modes Types of Instructions Assembler Directives Example Program

Memory Organization
Separate data & program memory On-chip program memory (8K on-chip for 8052) On-chip data memory (256 bytes of internal RAM for 8052) Off-chip program memory (up to 64K) Off-chip data memory (up to 64K) On-chip special function registers
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Register - Accumulator
8051 is an accumulator based Microcontroller It is an 8-bit register Accumulator can be the source or destination for logical operations and a number of special data movements Several functions apply exclusively to the accumulator(rotates,testing for zero etc.)
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Register DPTR
16-bit register namely data pointer Serves as a base register in
Indirect jumps Table look up instructions External data transfers

DPH(higher) & DPL(lower) are separate 8bit registers

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Register Stack Pointer

8-bit pointer register for stack Hardware stack with in internal RAM
for subroutine linkage parameter passing temporary variable storage saving status during ISRs

SP content indicates the address of the last byte pushed on to the stack Stack grows up from 08h onwards
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Register - PSW
It is a register with a group of status flags C-carry AC-auxiliary carry F0-flag0 RS1 & RS0 OV-overflow P-parity
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Addressing Modes
Immediate Mode specify data by its value
Data is contained in the instruction eg:MOV A,#n
mov a, #0 mov a, #11 mov a, #77h mov a, #11111111b ;put 0 in the accumulator a = 00000000 ; put 11 decimal in accumulator a = 00001011 ; put 77 hex in accumulator a = 01110111 ; put 11111111 binary in accumulator a = 11111111
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Addressing Modes
Direct Mode specify data by its 8-bit address
mov a, 70h Mov D0h, a ; copy contents of RAM at 70h to a ; put contents of a into PSW

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Addressing Modes
Register Addressing either source or destination is one of R0-R7
mov R0, a mov a, R0

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Addressing Modes
Register Indirect the address of the source or destination is specified in registers Uses registers R0 or R1 for 8-bit address:
mov 0xD0, #0 mov r0, #0x3C mov @r0, #3 ; use register bank 0 ; memory at 3C gets #3 ; M[3C] 3 ; dptr 9000h ; a M[9000]

Uses DPTR register for 16-bit addresses:

mov dptr, #0x9000 mov a, @dptr

Note that 9000 is an address in external memory

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Addressing Modes
Stack-oriented data transfer another form of register indirect addressing, but using SP
mov sp, #0x40 push 0x55 pop b ; ; ; ; Initialize SP SP SP+1, M[SP] M[41] M[55] b M[55]

M[55]

Note: can only specify RAM or SFRs (direct mode) to push or pop. Therefore, to push/pop the accumulator, must use acc, not a: push acc - is correct push a - is wrong
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Instruction set notations

Rn - registers R7-R0 of the currently selected
register bank direct - 8 bit internal data locations address

@Ri - 8 bit internal RAM location addressed indirectly through registers R1 or R0 #data - 8 bit constant included in the instruction #data16 - 16 bit constant included in the instruction
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Instruction set notations cntd..

addr16-16 bit destination address used by LCALL/LJMP(with in 64K) addr11-11 bit destination address used by ACALL/AJMP(with in 2K) rel-signed 8 bit offset byte used by SJMP and all conditional jumps bit-direct addressed bit in internal data RAM/SFR

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Instruction set
Arithmetic operations ADD A,Rn ADD A,direct ADD A,@Ri ADD A,#data ADDC ADDC ADDC ADDC A,Rn A,direct A,@Ri A,#data
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Instruction set cntd..

Arithmetic operations SUBB A,Rn SUBB A,direct SUBB A,@Ri SUBB A,#data INC INC INC INC A Rn direct @Ri
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Instruction set cntd..

Arithmetic operations
DEC DEC DEC DEC INC MUL DIV DA A Rn direct @Ri DPTR AB AB A

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Decimal Adjust
DA a ; decimal adjust a Used to facilitate BCD addition. Adds 6 to either high or low nibble after an addition to create a valid BCD number. Example: mov a, #0x23 mov b, #0x29 add a, b ; a DA a ; a

23 + 29 = 4C (wanted 52) a + 6 = 52

Note: This instruction does NOT convert binary to BCD!

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Instruction set cntd..

Logical operations
ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data

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Instruction set cntd..

Logical operations XRL A,Rn XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data
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Instruction set cntd..

RL A RLC A RR A RRC A CLR A CPL A SWAP A

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Rotate
Rotate instructions operate only on a rl a mov a, #0xF0 rl a ; a ; a 11110000 11100001
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Rotate through Carry

rrc a
C

mov a, #0A9h add a, #14h rrc a

; a ; a ; a

A9 BD (10111101), C 0 01011110, C 1

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Swap
swap a

mov a, #72h swap a

; a

27h

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Data Transfer Instructions

MOV dest, source 6 basic types:
MOV a, byte MOV byte, a MOV Rn, byte MOV direct, byte MOV @Rn, byte MOV DPTR, data16

dest source
;move byte to accumulator ;move accumulator to byte ;move byte to register of ;current bank ;move byte to internal RAM ;move byte to internal RAM ;with address contained in Rn ;move 16-bit data into data ;pointer

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Instruction set cntd..

Data transfer
MOV MOV MOV MOV A,Rn A,direct A,@Ri A,#data

MOV Rn,A MOV Rn,direct MOV Rn,#data

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Instruction set cntd..

Data transfer
MOV MOV MOV MOV MOV direct,A direct,Rn direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data
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MOV MOV MOV

Instruction set cntd..

Data transfer
MOV MOVC MOVC MOVX MOVX MOVX MOVX DPTR,#data16 A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A
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Instruction set cntd..

Exchange Instructions two way data transfer
XCH a, 0x30 ; a XCH a, R0 XCH a, @R0 XCHD a, R0 M[30] ; a R0 ; a M[R0] ; exchange digit

a[7..4] a[3..0]

R0[7..4] R0[3..0] Only 4 bits exchanged

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Instruction set cntd..

Program branching
JMP JZ JNZ CJNE CJNE CJNE CJNE RET RETI @A+DPTR rel rel A,direct,rel A,#data,rel Rn,#data,rel @Ri,#data,rel

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Instruction set cntd..

Program branching
DJNZ Rn,rel DJNZ direct,rel AJMP addr11 LJMP addr16 SJMP rel ACALLaddr11 LCALL addr16 NOP

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Instruction set cntd..

Boolean variable manipulation
CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL C bit C bit C bit C,bit C,/bit C,bit C,/bit
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Instruction set cntd..

Boolean variable manipulation
MOV MOV JC JNC JB JNB JBC C,bit bit,C rel rel bit,rel bit,rel bit,rel
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Assembler directives
Supply data to the program and control assembly process
Assemble code & data to specified sections Reserve space in memory for uninitialized variables Control the appearance of listings Initialize memory Assemble conditional blocks Specify libraries from which assembler can obtain macros Examine symbolic debugging information
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Directives cntd..
For storage control
ORG END DB DW value [value] value value

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Directives cntd..
Listing control
LIST ON LIST LIST OFF NOLIST NLIST

Others
EQU INCLUDE value filename
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 EQU Used to create symbols that can be used to represent registers, numbers, and addresses
LIMIT VALUE SERIAL COUNT MY_VAL EQU EQU EQU EQU EQU 2000 LIMIT 200 + 'A' SBUF R5 0x44 Registers, numbers, addresses

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System Defaults
Default file extensions
asm obj lst lib tsk hex s19 - input to the assembler - output from the assembler - listing file - library file - executable object code - Intel hex - Motorola s19
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System Defaults
Number base designation
Binary - B Octal - O or Q Decimal - D or no base designation Hex -H ASCII - Single or double quotes X or X

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Example program
org start: cpl call sjmp sjmp mov mov djnz djnz ret 8000h p1.7 delay start sleep r0,#0ffh r1,#0ffh r1,loop1 r0,loop2
; my code originates from 8000h the ; first External RAM address
; complement the Port1 7th Line which connected to LED ; call a subroutine to generate delay between Complements ; repeat the process ; if the program loop is over (never for this case) then wait in infinite loop ; my delay subroutine starts with var1 = 255 ; var2 = 255 ; var2 = var2 -1 , if var2 != 0 then loop ; if var2==0 then var1 = var1-1 and check if var1 != 0, if not reload var2 = 255 ; if a time of approximately (255 * 255 * 2) + 4 Clock cycles elapsed ; then you go back to main ; for a 89C52 with 11.0592 MHz Clock will generate a delay of approx 140 milliseconds ; delay = 1 / (11.0592 MHz /12 ) * ((255 * 255 * 2) + 4) = 1.085 Micro Seconds * 130054 = 140 ms

sleep delay loop2 loop1

end

; information to Assembler to end the assembling process

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