01

CMOS Circuit and Layout Design
Module Leader :
ACTP VSD402T
Module Objectives
This module is concerned with the design and analysis of CMOS digital circuit design. Design techniques utilizing CMOS technology will be mainly focused. It is expected that the systematic coverage of CMOS IC design techniques in the module will enhance the following skills for the students. 1. Learn state of the art CMOS VLSI system and circuit design. 2. Provides the tools to design common CMOS digital Circuits on a silicon
chip, given a set of specifications. 3. Provides insight into the various trade-offs between noise, power, speed, area, etc., that go into the design. 4. Emphasizes on the current trends adopted in semiconductor industry for CMOS digital design.
M.S. Ramaiah School of Advanced Studies
ACTP VSD402T
Module Resources
Module Notes Reference Text books: 1. Sung Kang and Yusuf Leblebici, CMOS digital integrated circuits, third
2. 3. 4. 5.
edition, McGraw Hill, 2002. R. Jacob Baker, Harry W. Li, David E. Boyce, CMOS Circuit Design, Layout, and Simulation, John Wiley and Sons, 1997, ISBN:0-78033416-7 R. L. Geiger, P. E. Allen and N. R. Strader, "VLSI Design Techniques for Analog and Digital Circuits," McGraw-Hill Publishing Company, New York, 1990 J. Rabaey, Digital Integrated Circuits-A design perspective, 2nd edition, 2005, PHI Neil H. E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design -A Systems Perspective- (4th ed.), Addison Wesley, 2001
Web Resources: foghorn.cadlab.lafayette.edu/~nestorj/ www.sigda.org/ http://ecen.okstate.edu/hutchen/classnotes/5363/oldlink.htm
ACTP VSD402T
Teaching and Learning Methods

Lecture Sessions Practical case studies Demos Lab session Homework/assignments
Tools
Cadence Virtuoso Suite
ACTP VSD402T
Module Evaluation
Assignment 60% Quiz 10% Exam 30%
Session 1
Introduction to IC Design
Session Speaker N. Venu Gopal
ACTP VSD402T
Session Objectives
To understand the concepts of
Transistor evolution and technology trends IC design methodologies Design styles

Full custom Standard cell Gate-array Macro-cell FPGA Combinations
ACTP VSD402T
Introduction
1906 1947
Audion (Triode), 1906 Lee De Forest
First point contact transistor (germanium), 1947 John Bardeen and Walter Brattain Bell Laboratories
ACTP VSD402T
Introduction
1958 1997
First integrated circuit (germanium), 1958 Jack S. Kilby, Texas Instruments Contained five components, three types: transistors resistors and capacitors Intel Pentium II, 1997 Clock: 233MHz Number of transistors: 7.5 M Gate Length: 0.35 9
ACTP VSD402T
Transistor Revolution
Transistor Bardeen (Bell Labs) in 1947 Bipolar transistor Schockley in 1949 First bipolar digital logic gate Harris in 1956 First monolithic IC Jack Kilby in 1959 First commercial IC logic gates Fairchild 1960 TTL 1962 into the 1990s ECL 1974 into the 1980s
10
ACTP VSD402T
MOSFET Technology
MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935 CMOS 1960s, but plagued with manufacturing problems (used in watches due to their power limitations) PMOS in 1960s (calculators) NMOS in 1970s (4004, 8080) for speed CMOS in 1980s preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K, strained silicon,
11
ACTP VSD402T
Moores Law
In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i.e., grow exponentially with time). Amazingly visionary million transistor/chip barrier was crossed in the 1980s.

2300 transistors, 1 MHz clock (Intel 4004) - 1971 16 Million transistors (Ultra Sparc III) 42 Million, 2 GHz clock (Intel P4) - 2001 140 Million transistor (HP PA-8500)
12
ACTP VSD402T
Moores Law in Microprocessors

# transistors on lead microprocessors double every 2 years
1000 100 Transistors (MT) 10 1 0.1 0.01 0.001 1970 8085 8086 8080 8008 4004 1980 1990 Year 2000 2010
Courtesy, Intel
13
2X growth in 1.96 years!
486 386 286
P6 Pentium proc
ACTP VSD402T
Evolution in DRAM Chip Capacity

100000000
human memory human DNA

64,000,000
10000000
4X growth every 3 years!

1,000,000
16,000,000 4,000,000
0.07 Qm
0.1 Qm
K b i t c a p a c it y /c h ip
1000000
0.13 Qm
100000
book
16,000 4,000
256,000 64,000
0.18-0.25 Qm
0.35-0.4 Qm
10000
0.5-0.6 Qm
0.7-0.8 Qm
1000 256 100 64 10 1980
1,000
1.0-1.2 Qm 1.6-2.4 Qm
encyclopedia 2 hrs CD audio 30 sec HDTV
page
1983 1986 1989 1992 1995 1998 2001 2004 2007 2010
Year
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ACTP VSD402T
Die Size Growth

Die size grows by 14% to satisfy Moores Law
100
Die size (mm)
10 8080 8008 4004 1 1970 1980 8086 8085 286
386
P6 486 Pentium proc
~7% growth per year ~2X growth in 10 years
1990 Year
2000
2010
Courtesy, Intel
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ACTP VSD402T
Clock Frequency
Lead microprocessors frequency doubles every 2 years
10000 1000 Frequency (Mhz) 100 486 10 1 0.1 1970 8085 8086 286 8080 8008 4004 1980 1990 Year 2000 2010
Courtesy, Intel
16
2X every 2 years
P6 Pentium proc 386
ACTP VSD402T
Power Dissipation
Lead Microprocessors power continues to increase
100 P6 Pentium proc 10 8086 286 1 8085 8080 486 386
Power (Watts)
8008 4004
0.1 1971 1974 1978 Year 1985 1992 2000

Courtesy, Intel
Power delivery and dissipation will be prohibitive

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ACTP VSD402T
Why Scaling?
Technology shrinks by ~0.7 per generation With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly Cost of a function decreases by 2x But
How to design chips with more and more functions? Design engineering population does not double every two
years
Hence, a need for more efficient design methods

Exploit different levels of abstraction
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ACTP VSD402T
Major Design Challenges

Microscopic issues ultra-high speeds power dissipation and

supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Year 1997 1998 1999 2002 Tech. (nm) 350 250 180 130
Macroscopic issues time-to-market design complexity

(millions of gates) high levels of abstractions reuse and IP, portability systems on a chip (SoC) tool interoperability
Complexity Frequency 3 Yr. Design Staff Size 13 M Tr. 20 M Tr. 32 M Tr. 130 M Tr. 400 MHz 500 MHz 600 MHz 800 MHz 210 270 360 800
Staff Costs $90 M $120 M $160 M $360 M

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ACTP VSD402T
Technology Evolution
International Technology Roadmap for Semiconductors
2003 data
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ACTP VSD402T
Driving force: Economics (1)

Traditionally, the cost/function in an IC is reduced by 25% to 30% a year. To achieve this, the number of functions/IC has to be increased. This demands for:
Increase of the transistor count Decrease of the feature size (contains the
area increase and improves performance) Increase of the clock speed
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ACTP VSD402T
Driving force: Economics (2)

Increase productivity:
Increase equipment throughput Increase manufacturing yields Increase the number of chips on a wafer:
reduce the area of the chip: smaller feature size & redesign Use the largest wafer size available
Example of a cost effective product (typically DRAM): the initial IC area is reduced to 50% after 3 years and to 35% after 6 years.
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ACTP VSD402T
VLSI Technology and Design Drivers

Less AREA, more COMPACTNESS at all system levels Less POWER CONSUMPTION Fewer CHIPS/COMPONENTS per board and system Higher RELIABILITY, due to improved on-chip interconnects HIGHER SPEED due to reduced interconnect length Significant COST REDUCTIONS
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ACTP VSD402T
Integrated Circuit Technologies

Why does CMOS dominate? other technologies
passive circuits III-V devices Silicon BJT
CMOS dominates because: Silicon is cheaper preferred over other materials physics of CMOS is easier to understand CMOS is easier to implement/fabricate CMOS provides lower power-delay product CMOS is lowest power can get more CMOS transistors/functions in same chip area BUT! CMOS is not the fastest technology! BJT and III-V devices are faster
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ACTP VSD402T
CMOS Technology Trends

Variations over time

# transistors / chip: increasing with time power / transistor: decreasing with time (constant power density) device channel length: decreasing with time power supply voltage: decreasing with time
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ACTP VSD402T
Todays Design Trends

Source: Prof. Rabay, UCBerkeley
K
Transistors
90nm 0.13um 0.18um 0.25um 0.35um 0.5um 0.8um 1um 1.5um 2um 3um
1,000,000 100,000 10,000 1,000 100 10 1
Time-To-Market
120% 100% 80% $1000 $10000
Fabrication Cost
60% 40% 20%
$Million 0 3 6 9 12 15 Months Late

Source: MIPS Technologies
Profit
$100
$10 0% -20% $1
1960
1970
1980
1990
2000
2010
Source: www.icknowledge.com
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ACTP VSD402T
What do designers really care about?

Design Objectives:

Power (dynamic/static) Timing (frequency) Area (cost/yield) Yield (cost) Manufacturing technology Leakage power Interconnect delay Variability Reliability
Challenges:
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ACTP VSD402T
Circuit Entities
NMOS transistor Metal interconnects
How do you manufacture them?
28
ACTP VSD402T
How do ICs get manufactured?

UV light Mask
oxygen Silicon dioxide Silicon substrate photoresist exposed photoresist oxide
Oxidation (Field oxide)
Exposed Photoresist Mask-Wafer Coating Alignment and Exposure Photoresist
Photoresist Develop
Dopant gas Ionized CF4 gas photoresist oxide Ionized oxygen gas oxide oxygen gate oxide Silane gas polysilicon
Ionized CCl4 gas oxide
Oxide Etch
Scanning ion beam
Photoresist Strip
Oxidation (Gate oxide)

silicon nitride
Polysilicon Deposition
Contact holes
Polysilicon Mask and Etch

Metal contacts G drain D S
G ox S D S
top nitride G D S G D S G D
Ion Implantation
Active Regions
Nitride Deposition
Contact Etch
Metal Deposition and Etch 29
[Check out this too http://www.appliedmaterials.com/HTMAC/animated.html]

ACTP VSD402T
And the end result is:
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ACTP VSD402T
CMOS scaling theory
critical dimension
Year CD (nm)
98
00
02
04 90
07 65
10 45
13 32
16 22
19 16
250 180 130
How does scaling impact transistor and interconnect performance? How does scaling continuously present new challenges to physical design? And how does it make some techniques obsolete What is the fundamental limits to scaling (how far can we go)?
31
ACTP VSD402T
CMOS scaling theory

active
[ITRS03] [Moore, ISSCC03]
leakage
gate delay global (no repeaters) local (scaled) global wires (repeaters)
32
ACTP VSD402T
How to cope with complexity?

By applying:
Rigid design methodologies Design automation
Rigid Design Methodologies
Design Automation (CAE Tools)
Successful Design
33
IC Design Methodology and Design Styles
ACTP VSD402T
Design Methodology
Specification Trade-offs Design domains - abstraction level Top-down - Bottom up Schematic based Synthesis based Getting it right Simulation and verification Lower power Design styles
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ACTP VSD402T
Specification
A specification of what to construct is the first major step. Compromise between what is wanted and what can be made
Requires extensive experience to define best compromise
A detailed specification must be agreed upon with the system people. Major changes during design may result in significant delays. Requirements must be considered at many levels
System, sub-system, Board, Hybrid, IC
Specifications can (must) be verified by system simulations. Specification is 1/4 - 1/3 of total IC project !.
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ACTP VSD402T
Trade offs
Partitioning Integration Tools Technology Availability Speed Time Schedule Reliability Man power Packaging
Testing Chip size
Development costs Power
Production costs
Radiation hardness
37
ACTP VSD402T
Design Domains
Gajski chart
Structural
Processor, memory ALU, registers Cell Device, gate Transistor
Behavioral
Program State machine Module Boolean equation Transfer function
Masks Gate Functional unit Macro IC
Geometric
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ACTP VSD402T
Abstraction Levels and Synthesis

Architectural level
Behavioral level
Logic level
0 0 0 State 0
Circuit level
Layout level
For I=0 to I=15 Sum = Sum + array[I]
Architecture synthesis Structural level

Memory Control
Logic synthesis
Circuit synthesis
Layout synthesis
+ (register level) Clk (Library)
Silicon compilation (not a big success)
Use of digital libraries And Place and route tools
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ACTP VSD402T
Top - down design

Choice of algorithm (optimization) Choice of architecture (optimization) Definition of functional modules Definition of design hierarchy Split up in small boxes - split up in small boxes - split up in small boxes Define required units ( adders, state machine, etc.) Floor-planning Map into chosen technology (synthesis, schematic, layout)
(change algorithms or architecture if speed or chip size problems)
Behavioral simulation tools
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ACTP VSD402T
Bottom - up
Build gates in given technology Build basic units using gates Build generic modules of use Put modules together Hope that you arrived at some reasonable architecture Gate level simulation tools Old fashioned design methodology a la discrete logic
Comment by one of the main designers of a Pentium processor
The design was made in a typical top - down , bottom - up , inside - out design methodology
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ACTP VSD402T
Schematic based
Symbol of module defines interface Schematic of module defines function Top - down: Make first symbol and then schematic Bottom - up: Make first Schematic and then symbol
Basic gate Logic module
Symbol
Long and tedious
Schematic
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ACTP VSD402T
Synthesis based
Define modules and their behavior in a proper language (also used for simulation) Use synthesis tools to generate schematics (netlists)
always @(posedge clk) begin if (set) coarse <= #(test.ff_delay) offset; else if (coarse == count_roll_over) coarse <= #(test.ff_delay) 0; else coarse <= #(test.ff_delay) coarse + 1; end
Only possible way to make designs with millions of gates
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ACTP VSD402T
Getting it right - Simulation

Simulate the design at all levels (transistor, gate, system) Analog simulator (SPICE) for transistor level Digital gate level simulator for gate based design Mixed mode simulation of mixed analog-digital design Behavioral simulation at system/module level (Verilog, VHDL) All functions must be simulated and verified. Worst case data must be used to verify timing Worst - Typical - Best case conditions must be verified Process variations, Temperature range, Power supply voltage Factor two variation to both sides ( speed: : 1 : 2) Use programming approach to verify large set of functions (not looking at waveform displays)
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ACTP VSD402T
Design styles
45
ACTP VSD402T
Full custom
Hand drawn geometry All layers customized Digital and analog Simulation at transistor level (analog) High density High performance Looong design time
Vdd
IN
Out
Gnd
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ACTP VSD402T
Standard cells
Standard cells organized in rows (and, or, flip-flops,etc.) Cells made as full custom by vendor (not user). All layers customized Digital with possibility of special analog cells. Simulation at gate level (digital) Medium- high density Medium-high performance Routing Reasonable design time
Cell
IO cell
47
ACTP VSD402T
Gate-array
Predefined transistors connected via metal Two types: Channel based, Sea of gates Only metal layers customized Fixed array sizes (normally 5-10 different) Digital cells in library (and, or, flip-flops,etc.) Simulation at gate level (digital) Medium density Medium performance Reasonable design time
Sea of gates Channel based Oxide isolation
Gate isolation
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ACTP VSD402T
Gate array example

NAND 2 gate Use where ever possible transistors in series Isolate to neighbors using transistors biased to be off If extremities connected to ground or power then this can be used in neighbor cell.
Vdd NAND gate using gate isolation
Vdd A B PMOS B Out A Out
NMOS
Gnd
Can in principle be used by adjacent cell Gnd
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ACTP VSD402T
Macro cell
Predefined macro blocks (Processors, RAM,etc) Macro blocks made as full custom by vendor ( Intellectual Property blocks = IP blocks) All layers customized Digital and some analog (ADC) Simulation at behavioral or gate level (digital) High density DSP processor High performance LCD RAM Short design time cont. Use standard on-chip busses ADC ROM System on a chip (SOC)
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ACTP VSD402T
FPGA = Field Programmable Gate Array

Programmable logic blocks Programmable connections between logic blocks No layers customized (standard devices) Digital only Low - medium performance (<50 - 100MHz) Low - medium density (up to ~100k gates) Programmable: SRAM, EEROM, Flash, Anti-fuse, etc Easy and quick design changes Cheap design tools Low development cost High device cost NOT a real ASIC
(Application Specific Integrated Circuit)
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ACTP VSD402T
Comparison
FPGA Density Flexibility Analog Performance Design time Design costs Tools Volume Low Low (high) No Low Low Low Simple Low
Gate array Medium Low No Medium Medium Medium Complex Medium
Standard cell Medium Medium No High Medium Medium Complex High
Full custom High High Yes Very high High High Very complex High
Macro cell High Medium Yes Very high Medium High Complex High
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ACTP VSD402T
Summary
Transistor evolution and technology trends IC design methodologies Design styles

53

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CMOS Circuit and Layout Design

M.S. Ramaiah School of Advanced Studies

 Web Resources:  foghorn.cadlab.lafayette.edu/~nestorj/  www.sigda.org/  http://ecen.okstate.edu/hutchen/classnotes/5363/oldlink.htm

M.S. Ramaiah School of Advanced Studies

Teaching and Learning Methods

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

Audion (Triode), 1906 Lee De Forest

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

Moores Law in Microprocessors

2X growth in 1.96 years!

486 386 286

M.S. Ramaiah School of Advanced Studies

Evolution in DRAM Chip Capacity

human memory human DNA

4X growth every 3 years!

1000 256 100 64 10 1980

encyclopedia 2 hrs CD audio 30 sec HDTV

Die Size Growth

Die size (mm)

10 8080 8008 4004 1 1970 1980 8086 8085 286

P6 486 Pentium proc

~7% growth per year ~2X growth in 10 years

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

0.1 1971 1974 1978 Year 1985 1992 2000

Power delivery and dissipation will be prohibitive

 Hence, a need for more efficient design methods

M.S. Ramaiah School of Advanced Studies

Major Design Challenges

 Macroscopic issues  time-to-market  design complexity

Staff Costs $90 M $120 M $160 M $360 M

M.S. Ramaiah School of Advanced Studies

M.S. Ramaiah School of Advanced Studies

Driving force: Economics (1)

M.S. Ramaiah School of Advanced Studies

Driving force: Economics (2)

M.S. Ramaiah School of Advanced Studies

VLSI Technology and Design Drivers

M.S. Ramaiah School of Advanced Studies

Integrated Circuit Technologies

M.S. Ramaiah School of Advanced Studies

CMOS Technology Trends

M.S. Ramaiah School of Advanced Studies

Todays Design Trends

1,000,000 100,000 10,000 1,000 100 10 1

60% 40% 20%

$Million 0 3 6 9 12 15 Months Late

M.S. Ramaiah School of Advanced Studies

What do designers really care about?

M.S. Ramaiah School of Advanced Studies

How do you manufacture them?

M.S. Ramaiah School of Advanced Studies

How do ICs get manufactured?

Oxidation (Field oxide)

Exposed Photoresist Mask-Wafer Coating Alignment and Exposure Photoresist

Ionized CCl4 gas oxide

Oxidation (Gate oxide)

Web Resources: foghorn.cadlab.lafayette.edu/~nestorj/ www.sigda.org/ http://ecen.okstate.edu/hutchen/classnotes/5363/oldlink.htm

Hence, a need for more efficient design methods

Macroscopic issues time-to-market design complexity

Behavioral simulation tools