Professional Documents
Culture Documents
Process variations
Arise due to perturbations in the fabrication process Resulting in variations in the nominal values of parameters
Gate length Gate oxide thickness Dopant concentration Interlevel dielectric thickness Interconnect height and width.
Interdie variations
Die-to-die variations wafer-to-wafer variations lot-to-lot variations Affect all the devices on the same die in the same way For example, they may result in the gate lengths of all the transistors on any die to be larger than or smaller than the nominal value
Intradie variations/Mismatch
Variability within a single die Affect the different transistors differently on the same die For example they may result in some transistors having smaller oxide thickness, while others may have larger oxide thickness than the nominal Also known as local process variation and mismatch (LPVM)
Clock skew comparable to clock period, for the chips operating at GHz range Variations in data setup and hold times in flip-flops and registers Mismatch effects are imposing a stringent tradeoff between the speed and yield of high performance digital ICs
Process variations1
Process variations2
Nano-scale MOSFETs
When the conventional MOSFET is being taken into nano dimensional world many new techniques are being added in order to realize the MOSFET with significant performance improvement Currently various stress enhancements are considered by semiconductor industries Dual stress Laser annealing is the feasible option to get ultra low junction depths As new techniques are getting added the sources of variations are also increasing
LPVM affects
ICs And ICs have transistors, resistors and capacitors
Influence of LPVM on resistor Influence of LPVM on capacitors Influence of LPVM on MOSFETs
CMOS resistors
Resistors
Well resistors Metal resistors Diffused resistors Poly resistors
Resistor value
Formula for resistance (R)= L/A = L/(W.t) = Rsh.(L/W) Where Rsh = (/t) R depends on dimensions variations in dimensions changes R Differential amplifiers we need two similar resistors (R1 and R2) LPVM makes R1 and R2 different
Common mode gain etc changes
Dimension changes
Variation in dimensions
Photolithographic inaccuracies Line width control: A measure of dimensional variation introduced by photolithographic process Scenario improves for feature sizes more than 5 m
Example
R = R + (CL/W) + Rsh Given width 2 m, CL - 0.25 m, variation in Rsh - 25% Variation in R is 37.5% If width is 10 m then variation R is 27.5%
10
-5
-10
Variation means that a process does not produce the same result every time Some variation will exist in all processes
10
20
30
40
50
Managing by the average doesnt tell the whole story. The average and the variation together show whats happening.
10
20
30
40
50
Sigma level measures how often we meet (or fail to meet) the requirement(s) of our customer(s).
% Bad
69.1% 30.9% 6.7% 0.62% 0.023% 0.00034%
Observations
Lower widths larger variations Higher resistance larger variations Use larger width Use smaller resistances?!
Common practice is that a resistor with long length (for high resistance) is broken into shorter resistors in series
Capacitors in CMOS
Current CMOS technology provides various capacitance options
poly-to-poly capacitors, metal-to-metal capacitors, MOS capacitors, and junction capacitors
Variation > 20 %
Nanometer dimensions More number of complicated processing steps Process variations - no more negligible
Resulting electrical
Optimum process
Determine the most stable process condition The aim is to quantify the amount of variations at the device taking into account the individual process variations The process condition leading to the least amount of variation at the device is the most stable process
Process parameters Device performance
Variability Yield