Power Converters and Drives Lab - A Research Overview

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
1
Power Converters and Drives Lab
-a Research Overview
Prof. K. Gopakumar
Centre for Electronics Design and Technology
Indian Institute of Science, Bangalore
INDIA: 560012
2
A1
S
1
S
4
S
5
S
2
B1
S
3
S
6
C1
V
dc

Conventional two-level inverter structure
Induction
motor
3
V
dc
/2
-V
dc
/2
0
C1
wt

as
V
bs
V
V
cs
SVPWM for conventional two-level inverter
4
R
e
f
e
r
e
n
c
e

s
i
g
n
a
l
s

a
n
d

c
a
r
r
i
e
r

(wt)
v
AN
v
BN
v
CN 0.5
-0.5
V

a
0

V

b
0

V

c
0

V
dc
/2
V
d
c
/2
V
dc
/2
-V
dc
/2
-V
dc
/2
-V
dc
/2
V
t
/2
3 /2
2
Pole voltage waveforms in conventional two-level inverter
6
Multilevel inverters
Topologies
Inverter topologies cascading two level inverters
Inverter topologies with open-end IM drive
Inverter topologies with asymmetric DC link voltages
Multilevel inverter topologies for common mode voltage elimination
Two-level inverter scheme with common mode voltage elimination
Higher level of multilevel inverter scheme
DC-link capacitor voltage balancing winding induction motor drive
Three-level structure with single power supply
PWM signal generation for multilevel inverter
A Space Phasor Based Self Adaptive Current Hysteresis
Controller
Multi-phase (six-phase) and multi motor drive
Sensorless control scheme for IM drive
12-sided polygonal voltage space phasor generation.
Presentation outline
7
Multilevel inverters
8
Synthesis of higher voltage levels using power devices of lower
voltage ratings

Increased number of voltage levels which leads to better voltage
waveforms and reduced Total Harmonic Distortion (THD) in voltage

Reduced switching stresses on the devices

Advantages of multilevel inverters over the two-level
inverters

9
C A
o
S11
S12
S1
3
S14
S21
S24
S23
S22
S31
S32
S33
S34
B

C1
C2
V
dc
+
_
3-ph
Ac mains
Neutral clamped inverter topology for 3-level inversion
The neutral point fluctuates as the capacitors C
1
and C
2
carry load currents
Bulkier capacitors are needed to check the neutral point fluctuation
PWM strategies aim to balance the neutral point dynamically
10
Dual Inverter fed induction motor with open end winding
11
a
V
dc
/4
V
dc
/4
o
a
b
c
b
c
Inverter-I Inverter-II
3-ph IM with open wdg.
The neutral point of the conventional IM is opened and is fed from both sides.
The DC - bus voltage is V
dc
/2 .

12
Space phasor locations for Inverter-I (Left) and Inverter-II (Right)
6 (+-+)
(-++) 4 1 (+--)
2 (++-)
(-+-) 3
(--+) 5
7 (+++)
(---) 8
(-++) 4
1 (+--)
2 (++-)
(-+-) 3
(--+) 5
6 (+-+)
7 (+++) (---) 8
V
dc
/2
V
dc
/2
13
Voltage space phasor combinations from the dual inverter scheme
A total of 64 space phasor combinations are available

14
Dual Inverter fed induction motor with open end winding with isolated DC
power supply
Inverter - 2

c
a
b
IM with
open-end
winding
b
a
c

Inverter - 1
V
dc
/2
V
dc
/2
Triplen harmonic suppression is achieved through the transformer isolation.

15
A new three-level inverter circuit topology cascading
two two-level inverters

16
The power circuit configuration of a three-level inverter
cascading conventional two two-level inverters
17
Space vector locations of the proposed three-level inverter
Similar to the conventional three-level inverter
18
The power Bus structure is simple
Can work as a conventional 2-level inverter in the lower voltage range
The total VA rating of the the transformers is the same as that of the NPC
configuration
High voltage fast recovery diodes are not needed
Three devices need to support the total DC bus voltage

Salient features of the proposed three-level inverter configuration
19
Pole Voltage waveforms of Inverter-1 (Top) and Inverter-2 (Bottom) Phase voltage
Phase current at no-load
|V
sr
| = 0.4V
dc
A
2
V
dc
/2 = 150V
V
dc
/2 = 150V
O
A
1
Experimental results: lower modulation range
20
|V
sr
| = 0.6V
dc
Experimental results: higher modulation range
21
|V
sr
| = V
dc
(Over-modulation)

Experimental results: over modulation range
22
A new five-level inverter circuit topology cascading two
three-level inverters
23
Introduction
An inverter system for open-end winding induction motor
is presented.
Open-end winding IM is fed by two three-level inverters
The 3-level inverters are realised by cascading two 2-level
inverters
This inverter scheme results in space phasor locations
similar to a conventional Five-level Inverter
24
V
dc
/4
V
dc
/4
Inverter A
+
+
S
12
S
16
S
15
S
13
S
22
S
26
S
24
S5
S
23
S
21
S
25
INV 2
INV 1
S
11
S
14
-
C1
-
C2

C4
S
3
2
S
3
6
S
3
5
S
3
3
S
42
S
46
S
44
S
43
S
4
5
A4
B4
INV 4
INV 3
Inverter B
S
41
S
34
S
31
-
+
V
dc
/4
-
+
V
dc
/4
C3
B3 A3 C3
C4
IM
O O
A2
A1 B1 C1
B2
C2
The schematic for the proposed five-level drive
Inverter A and Inverter B are 3-level inverters
Each three level is formed by cascading two 2-level inverters

INV1,INV2
Inverter A
INV3,INV4
Inverter B
25
V
dc
/4
V
dc
/4
Inverter A
+
+
S
12
S
16
S
15
S
13
S
22
S
26
S
24
S5
S
23
S
21
S
25
INV 2
INV 1
S
11
S
14
-
C1
-
C2
O
A2
A1 B1 C1
B2
C2
V
A2O

The 3-level inverter topology
Levels in A-leg
0 when S
24
is on

( V
A2O
)
V
dc
/4 when S
21
and S
14
on

V
dc
/2 when S
21
and S
11
on

The 2-level inverters have DC-link of
This 3-level structure does not require neutral point clamping
diodes
V
dc
/4
26
All legs of the three-level inverter can independently take
any of the three levels
when inverter-A and inverter-B are switched independently
5-levels can be generated across the winding.
V
A20
V
A40
V
A2A4
= V
A20
- V
A40

0
0
0
V
dc/4
V
dc/2

V
dc/2
V
dc/4

0
0
0

-V
dc/2
( L1)
-V
dc/4
( L2)
0 ( L3)
V
dc/4
( L4)

V
dc/2
( L5)

* for the first three levels only Inverter-B is switching
Realization of five voltage levels across motor phases
27
Space vector representation of the proposed Drive
Similar to a five-level inverter
125 space vector combinations
96 sectors
61 locations
Four layers
28
The Modulation scheme
Multi-carrier PWM method is used
Four triangular carriers
20% third harmonic added to the 3 reference signals
A discreet DC shift is given to the reference signals
depending on the speed range
With this modulating scheme the inverter starts with
2-level operation and then moves to 3-level, 4-level
and 5-level operation as speed increases

29
The reference wave set is placed at
the middle of the carrier set
Three levels are involved, therefore
three-level waveform
Conventional SPWM For Low modulation index

SPWM for the proposed Drive
the middle of the lowermost carrier
Only two levels are involved, therefore
two-level waveform
Only INV3 is switching ( the top
2-level inverter of Inverter-B)
hence losses are only due to INV3
30
Conventional SPWM
For next speed range
(V
c
/2< V
m
<Vc )
V
c
: Peak to peak amplitude of the carrier

V
m
: Peak amplitude of the reference wave

the middle of the lower two carriers
Only INV4 and INV3 are switching
(2-level inverters of Inverter-B)
losses are only due to Inverter-B
31
Conventional SPWM
For next speed range
(V
c
<V
m
<3V
c
/2 )
Five levels are involved, therefore
five-level waveform
All the 2-level inverters have to
be switched
the middle of second carrier ( C2)
Four levels are involved,
therefore four-level waveform
Only INV2, INV4 and INV3 are
switching
INV1 is not switching
32
For the maximum speed range ( V
m
> 3V
c
/2 )
The reference set is at the center of the carrier set
All the Five-levels are involved
All the inverters have to be switched
33
2-Level operation
Phase voltage shows 2-level
waveform
Inverter-B,is switching
between Vdc/2 and Vdc/4
( 200V and 100V)
This is due to the switching
of INV3 ( top inverter of
Inverter-B). INV4 is
clamped.
Inverter-A is clamped to zero
Motor phase voltage during 2-level operation
Pole voltage of Inverter-B during 2-level operation
Pole voltage of Inverter-A during 2-level operation
34
3-Level operation
Motor Phase Voltage
shows 3-level waveform
Inverter-B is switching as 3-level
inverter (200V,100V,0V)
Both the 2-level inverters of
Inverter-B ( INV3 and INV4 are
switching)

Inverter-A still clamped to zero
Pole voltage of Inverter-B during
3-level operation
35
4-Level operation
Motor Phase Voltage
Inverter-B is switching as 3-level
inverter (200V,100V,0V)
Inverter-A is switching as 2-level
inverter (100V,0V)
This is due to the switching of
INV2( bottom 2-level inverter )
Pole voltage of Inverter-B
Pole voltage of Inverter-A
36
5-Level operation
Motor Phase Voltage
Inverter-B is switching as 3-
level inverter (200V,100V,0V)
Inverter-A is also switching as
3-level inverter (200V,100V,0V)
Pole voltages of Inverter-A and Inverter B
Showing the phase relation (simulation results)
Pole voltages of Inverter-A (top) and
Inverter B (bottom) [ experimental results]

37
Motor phase current
2-level operation
3-level operation
4-level operation
5-level operation
38
Salient Features
Feeding the open-end winding induction motor by 3-level
inverters, results in voltage space phasors similar to a
5-level inverter
The three level inverters used are realised by cascading
Two 2-level inverters. This structure does not require neutral
Clamping diodes .
Compared with series connected H-bridge topology,
the proposed drive scheme uses less number of power
Supplies ( four against six required for H-bridge).
39
Open end winding IM drive (Three level operation) with a single DC
link
40
Dual Inverter fed induction motor with open end winding with isolated DC
power supply
Inverter - 2

c
a
b
IM with
open-end
winding
b
a
c

Inverter - 1
V
dc
/2
V
dc
/2
Triplen harmonic suppression is achieved through the transformer isolation.
All the 64 - space phasor combinations can be used in this case.
The transformers are bulky and expensive.
41
-V
dc
/ 2 - V
dc
/ 3 -V
dc
/ 6 0 V
dc
/ 6 V
dc
/ 3 V
dc
/ 2
8 7 8 4 8 5
8 3
1 1
2 2
3 3
5 8
3 8
4 8 7 8
8 6 5 4
3 4
4 4
5 5
6 6
4 5
4 3
6 8
8 2 8 1
5 6
7 7
8 8
1 3
4 1
1 8
2 8
5 7 5 2
3 6
6 4
1 5
2 4
6 5
6 3
7 5

3 7 3 2
4 7
3 5
2 6
3 1
2 5
2 3
7 3

1 7 1 4
1 6
4 6
5 1
4 2
7 4
6 1
7 1

1 2
6 7
5 3
6 2
2 1
7 6

2 7 7 2

Triplen harmonic contribution from various space- vector combinations (Twenty
combinations are available with a triplen harmonic content of zero)
42
Space phasor combinations with zero triplen harmonic contribution
43
Proposed power circuit schematic (switched neutral)
+
V
dc

-
3-ph Open-end
winding IM
Aux. Sw1
Aux. Sw2
Aux. Sw3
Aux. Sw4
Inv.1 Inv.2
C
1

C
2

Auxiliary switches SW 1 and SW 3 are opened when inverter-1 assume
states 7 or 8.( switched neutral)
Auxiliary switches SW 2 and SW 4 are opened when inverter-2 assume
states 7 or 8.
For safe combinations auxiliary switches are kept closed.
44
Space phasor combinations used in the proposed control strategy
Space phasor locations G,I,K,M,P,Q and R are forbidden.
For combinations at H,J,L,N,Q and S the auxiliary switches need not be opened ( safe
states).
Other combinations have a zero state at one end. Appropriate auxiliary switches are
opened to achieve triplen harmonic suppression
Title
45
Pole voltages of individual inverters and the phase voltage (middle)
with triplen content when |V
sr
| = 0.4V
dc

Actual motor phase voltage (left) and the motor phase current (right)
when |V
sr
| = 0.4V
dc

Experimental results
46
sr
| = 0.6V
dc
Actual motor phase voltage (left) and the motor phase current (right)
when |V
sr
| = 0.6V
dc

47
sr
| = 0.9V
dc

Actual motor phase voltage (left) and the motor phase current (right) when |V
sr
|
= 0.9V
dc

48
A Dual Two Level Inverter Scheme for an Open-end winding
Induction Motor Drive with a Single DC Power Supply and improved
DC bus Utilization

49
O
C
D
E
F
B
A
14
13
V
1

V
1
'
G
H
I K
L
M
N
S
18
17
16
15
V
2

V
2
'
8
The extreme vertices G, I, K, M, P and R are not switched.
The DC-bus utilization is lower by about 15%
Only 40 out of the 64 space vector combinations are used.
P
R
50

The triplen harmonic currents are denied a path by turning off the auxiliary
switches.

The auxiliary switch pairs toggle in this switching strategy with a fixed
frequency.

At a time only one inverter is connected to the DC link

The DC-bus utilization is enhanced by about 15% compared to the earlier
switching strategy.

Salient features of the switching strategy
51
(SW1,SW3) and (SW2, SW4) toggle at a fixed frequency
52
The motor phase voltage The motor phase current
|V
sr
| = 0.4V
dc
53
The triplen harmonic voltage
in (v
AO
- v
AO
)
Top trace: Voltage across the auxiliary switch
Bottom trace: Current through the auxiliary switch
|V
sr
| = 0.4V
dc
54
The motor phase voltage
The motor phase current
|V
sr
| = 0.7V
dc
The motor phase voltage with the earlier strategy
when |vsr| = 0.6V
dc

Experimental results: three-level operation
55
|V
sr
| = V
dc
(Over-modulation)

Experimental results: over modulation operation
56
The 12-step operation

57
Multi-level structures with asymmetric DC link voltages
58
A Multilevel Voltage Space vector Generation for an Open-end
winding Induction Motor Drive using a dual-inverter scheme with
Asymmetrical DC-link voltages

59

A dual-inverter fed open-end winding IM drive is proposed, with asymmetric
DC-link voltages (in the ratio 2:1).
In this scheme, 64 space vector combinations are distributed over 37 space vector
locations with 54 sectors.
The switching ripple is lesser compared to the earlier scheme i.e. with
equal DC-link voltages.
The motor phase voltage waveform exhibits either 2-level waveform,
3-level waveform or the 4-level waveform depending upon the motor speed.

Salient features of the proposed Drive
60
Inverter - 1
with asymmetric voltages showing individual space phasor combinations
(- + - ) 3
(+++) 7 8 (- - -)
1 (+- -)
2 ( ++ - )
( - + + ) 4
( - - + ) 5
6 ( + - + )
2 / 3 V
dc

(+++) 7
8 (- - -) 1 (+- -)
2 ( ++ - )
( - + + ) 4
( - - + ) 5 6 ( + - + )
(- + - ) 3
1 / 3 V
dc
Inverter - 2

c
a
b
IM with
open-end
winding
b
a
c

2/3V
dc

1/3V
dc

61
Space phasor combinations for asymmetrical voltage dual - inverter drive
64 space vector combinations
54 sectors
37 locations
three layers
62
Motor phase voltage (left) and the motor phase current (right)
when |Vsr| = 0.2V
dc
(2-level waveform)

Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the
triplen -harmonic content for |Vsr| = 0.2V
dc

63
The actual motor phase voltage and motor phase current when |Vsr| = 0.5 V
dc
(3-level waveform)
Normalized harmonic spectrum of the motor phase voltage illustrating
the absence of the triplen -harmonic content for |Vsr| = 0.5V
dc
64
the absence of the triplen -harmonic content for |Vsr| = 0.8V
dc

The actual motor phase voltage and motor phase current when |Vsr| = 0.8 V
dc
(4-level waveform)

65
The actual motor phase voltage and motor phase current when |Vsr| = V
dc
The harmonic spectrum of the motor phase voltage (showing the absence of the triplen
harmonic content) for |Vsr| = V
dc

66
The actual motor phase voltage and motor phase current during square wave ( 18 - step operation)

the absence of the triplen -harmonic content for 18-step operation
67
A Multilevel Inverter System for an Open-end Winding
Induction Motor
68
In the proposed scheme, a total of 512 voltage space vector combinations are
present, distributed over 91 space vector locations.
The three-level inverter in this scheme is realized by cascading two two-level
inverters.
In the lowest speed range, only one of the three inverters is switched. In the medium
speed range two inverters are switched and in the higher speed range, all the three
inverters are switched.
This feature ensures that the switching losses are reduced in the lower and the
middle range of speed.
The motor phase voltage shows a 2-level waveform in the lowest speed range, a 3-
level or a 4-level waveform in the medium speed range, a 5-level or a 6-level
waveform in the higher speed range.
This configuration needs three isolated power supplies.

The salient features of the proposed scheme
69
Schematic circuit diagram of the proposed inverter scheme
v
A2O
v
A3O

v
A2A3 =
v
A2O
v
A3O

0
0
2/5V
dc

2/5V
dc

4/5V
dc

4/5V
dc

1/5V
dc

0
1/5V
dc

1/5V
dc

0
0
-1/5V
dc

0
1/5V
dc

2/5V
dc

3/5V
dc

4/5V
dc

70
In the lower speed range, only inverter-3 is switched (2-level waveform)
In the medium speed range Inverter-2 and Inverter-3 are switched (3-level or 4-level waveforms)
In the higher speed range, all the inverters are switched. ( 5-level or 6-level waveform)
Space vector locations from the individual inverter structures
71
Resultant space vector locations when inverter-1 is inactive i.e. clamped to the state 8(---)
Combined space vector locations (inner layers)
72
A total of 91 vector locations with 8
3
= 512 space vector combinations organized into 5 layers
Combined space vector locations (outer layers)
73
Motor phase voltage Motor phase current
|V
sr
| = 0.12 V
dc
(Inner hexagon)

Inverter-3 is alone switched
Title
74
Motor phase voltage Motor phase current at no-load
|V
sr
| = 0.3V
dc
(Layer-2)

|V
sr
| = 0.48V
dc
(Layer-3)

Motor phase voltage
Motor phase current at no-load
Inverter-1 and inverter-2 are switched in these two layers
75
|V
sr
| = 0.65V
dc
(Layer-4)

|V
sr
| = 0.83V
dc
(Layer-5)

Motor phase voltage
All the three inverters are switched in these two layers
76
|V
sr
| = V
dc
(Over-modulation)

30 step operation

Motor phase voltage
All the three inverters are switched in these two cases
77
Seven-level voltage space phasor generation
scheme for an open-end winding induction
motor drive with asymmetric
dc link voltages
78
+
1
C
2
C
3
dc
V
6
dc
V
INV1
INV2
-
1
C
2
C
3
dc
V
6
dc
V
+
INV3
INV4
-
Induction
motor
Higher-level voltage waveforms can be synthesized when individual
inverters are supplied with unequal DC link voltages
Seven-level space phasor generation from a five-level inverter
DC link voltage of the top two-level inverters is V
dc
/3
DC link voltage of the bottom two-level inverters is V
dc
/6
+
-
+
-
Multi-level inverter configuration for induction motor with
open-end winding structure with asymmetric DC Links
79
Requires only four isolated power supplies

+
1
C
2
C
3
dc
V
6
dc
V
INV1
INV2
-
1
C
2
C
3
dc
V
6
dc
V
+
INV3
INV4
-
Induction
motor
+
-
+
-
Multi-level inverter configuration for induction motor with
open-end winding structure with asymmetric DC Links
80
O
V
dc
/2
V
dc
/6
Seven-level inverter configuration with asymmetric
dc link voltages
81
Seven-level voltage space phasor generation
82
343 space vector
combinations
127 space vector
locations
216 triangular
sectors
Space vector diagram of seven-level inverter
83
Comparison: proposed inverter scheme with
H-bridge inverter configurations
Proposed seven-
level inverter
H-bridge seven-level
inverter with symmetric
DC links
H-bridge inverter
asymmetric DC
links
Maximum
device rating
Top inverter: V
dc
/3
Bottom inverter:
Top devices V
dc
/6
Bottom devices V
dc
/2
V
dc
/6 V
dc
/3
Switches 8 per phase 12 per phase 8 per phase
DC link power
supplies
2 (V
dc
/3)
2 (V
dc
/6)

9 (V
dc
/3) 3 (2V
dc
/3)
3 (V
dc
/3)
Seven-level voltage space phasor generation scheme
84
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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163
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159
160
105
106
107
108
109
110
113
114
115
174
175
151
152
153
154
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156
157
29
210
212
214
216
97
98
99
100
101
102
103
143
144
146
148
150
145
147
149
211
213
215
194
195
196
197
1989
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181
182
183
184
185
186
187
188
189
190
191
130
131
192
193
161
162 172
173 171
112
111
158 104
A
B
C
axis o
axis |
216 sectors
6 layers
Over-modulation
In V/f mode, the length of
the reference space
vector is decided by the
speed command.
Space vector diagram of seven-level inverter
85
Phase-A voltage, phase-A current and common mode
voltage waveforms for M.I.= 0.14 (Layer 1 operation)
V
A2A4
I
A
V
OO
86
Phase-A voltage, phase-A current and common mode
voltage waveforms for M.I.= 0.28 (Layer 2 operation)
V
A2A4
I
A
V
OO
88
Phase-A voltage, phase-A current and common mode voltage
waveforms for modulation index 0.57 (Layer 4 operation)
V
A2A4
I
A
V
OO
89
V
A2A4
I
A
V
OO
90
V
A2A4
I
A
V
OO
91
Phase-A voltage and phase-A current waveforms for
modulation index 0.94 (over- modulation operation)
V
A2A4
I
A
93
Inverter operation under speed reversal:- Phase-A
voltage and phase-A current
V
A2A4
I
A
94
A High-Resolution Multi-Level Voltage Space Phasor Generation
for an Open-end Winding Induction Motor Drive

95
A topology for high resolution voltage space phasor generation
for an open-end winding induction motor drive is presented
Introduction
The open-end winding induction motor is fed from both ends
by two 3-level inverters with asymmetrical DC links
This results in voltage space phasors equivalent to
a conventional 9-level inverter
The 3-level inverters used in the proposed drive, are realised
by cascading two 2-level inverters
96
3/8V
dc
3/8V
dc

Inverter A
+
+
A2
S
12
S
16
S
15
S
13
S
22
S
26
S
24
S
23
S
21
S
25
INV 2
INV 1
S
11
S
14
-
C1
-
C2

C4
S
32
S
36
S
35
S
33
S
42
S
46
S
44
S
43
S
45
A4
B4
INV 4
INV 3
Inverter B
S
41
S
34
S
31
-
+
1/8V
dc
-
+
1/8V
dc
C3
B3 A3 C3
C4
IM
O O
B2
C2
A1 B1 C1
The power Circuit

Inverter A and Inverter B are formed by cascading 2-level inverters
INV1,INV2 Inverter A ||| INV3,INV4 Inverter B
INV1,INV2 3/8V
dc
INV1,INV2 1/8V
dc

Inverter A and
Inverter B are
3-level inverters
97
Inverter A
Levels in A-leg
( V
A2O

)

Inverter B
Levels in A-leg
( V
A4O

)
Levels in A-phase
of the machine
( V
AA
= V
A2O
- V
A4O
)

0
0
0
3/8
3/8
3/8
6/8
6/8
6/8

2/8
1/8
0
2/8
1/8
0
2/8
1/8
0

-2/8 L1
-1/8 L2
0 L3
1/8 L4
2/8 L5
3/8 L6
4/8 L7
5/8 L8
6/8 L9

The levels across the machine phase winding
98
217 Locations
384 Sectors
Space vector representation
9-levels in space vector
Amplitudes along :
0,1/8, V
dc
,2/8 V
dc
, 3/8 V
dc
,4/8 V
dc
,

5/8 V
dc
, 6/8 V
dc
,

7/8 V
dc
and V
dc
axis
axis
axis
99
the middle of the carrier set
Conventional SPWM
the middle of the lowermost carrier
Only two levels are involved, therefore
two-level waveform
Only INV3 is switching ( the top
2-level inverter of Inverter-B)
hence losses are only due to INV3
For Low modulation index
100
A progressive discreet DC shift in steps of Vc/2 is
given to the reference wave set as the speed increases
9-level operation for the maximum speed range
The inverter then moves through 3-level,4-level,5-level,
6-level,7-level,8-level and 9-level operation
101
INV1 and INV2 DC-link : 150V ( 3/8 V
dc
)
INV3 and INV4 DC-link : 50V ( 1/8 V
dc
)

Layer 1
Phase voltage 2-level
waveform
Pole voltage of Inverter-B
Only INV3 of Inverter-B
is switching in 2-level mode
( 100 V and 50V)
Experimental results :
102
Experimental results -Layer 2
waveform
Inverter-B in 3-level operation
Inverter-A not switching
( 100V, 50V and 0V)

103
waveform
Inverter-B in 3-level operation

Inverter-A starts switching in
2-level mode ( 100V and 0V)
104
waveform
Inverter-A in 2-level
operation
Inverter-B in
3-level mode
105
Experimental results -Max speed range
waveform
Inverter-A also in 3-level
operation ( 300V,150V,0V)
Inverter-B in
3-level mode ( 100V,50V,0V)
Inverter-A switching less
frequently than Inverter-B
106
The Current waveforms
During 8-level operation During 9-level operation
The Harmonic Spectrum of
the Phase Voltage During 9-level operation
107
Common mode voltages and its effect on induction
motor drive operation
108
A
o
S11
S12
S13
S14
S21
S24
S23
S22
S31
S32
S33
S34
B
C1
C2
V
dc
+
_
AO AN NO
BO BN NO
CO CN NO
v v v
v v v
v v v
= +
= +
= +
( )
NO AO BO CO
1
v v v v
3
= + +
Induction
Motor
N
a1
b1
c1
C
Common-mode Voltage Generation by a Multi-level VSI
109
Three-level inverter configuration with common mode voltage
elimination
110
PWM inverters generate high frequency, high amplitude
common mode voltages, which induces shaft voltage on the
rotor side
When the induced shaft voltage exceeds the breakdown voltage
of the lubricant in the bearings, result in large bearing currents
Problems associated: erosion of the bearing material, premature
mechanical failure of bearings leading to motor failure, increase
in total leakage current through the ground conductor resulting
into increased conducted EMI and false tripping of relays
PWM inverters which do not generate common mode
voltage are suggested as a solution to the above problems
Common mode voltages and its effects
111
elimination
112
A dual two-level inverter scheme with common mode
voltage elimination for an induction motor drive

113
S
41
A
1

B
1

C
1

S
12
S
16
S
14
S
13
S
11
S
15
INV 1
+
-
V
dc
/2
S
22
S
26
S
24
S
23
S
25
INV 2
IM
S
24
C
2

B
2

A
2

+
-
V
dc
/2
O O
Schematic of dual inverter fed open end winding induction
motor drive with isolated DC-links
114
A
B C
D
E F
O
o
|
A
B
C
D
E
F
O
o
|
INV1
INV2
Magnitude of space
Phasors : ( ) 2 V
dc
1
2
3
4
5
6
1
2
3
4
5 6
The voltage space vectors of the individual inverters
115
18
28
22,44
85
86
77
38
81 11, 33
56
82
87,78
43
67
88
74
73
55,66
24
14
74
16
17
15
25
75
26
27
34
76
35
36
37
46 21
45
47
31
41
71
48
58
32
72
51
52
57
42
61 68
62
83
53
63
12
64
23
54
13
65
A -phase
axis
A
B C
D
E F
G
H
I
J
K
L
M
N
P
Q
R
S
O
o
|
The voltage space vectors and space phasor
combinations of the dual inverter
116
Voltage space vector combinations producing zero common
mode voltage in the motor phase windings
117
S
41
A
1

B
1

C
1

S
12
S
16
S
14
S
13
S
11
S
15
INV 1
+
-
V
dc
/2
S
22
S
26
S
24
S
23
S
25
INV 2
IM
S
24
C
2

B
2

A
2

O
Schematic of dual inverter fed open end winding induction
motor drive with single DC-links
118
S
24
15
26 35
51
42
62
53
64
13
A -phase
axis
G
H
I
J
K
L
M
N
P
Q
R
o
|
46
31
O
1
2
3
4
5 6
11
22
33
44
55 66
77 88
Voltage vectors without triplen contribution
119
S
15
35
51
53
13
A -phase
axis
G
H
I
J
K
L
M
N
P
Q
R
o
|
31
O
1
2
3
4
5 6
11
33 55
55
11
33
( ) 2 V 3
dc
The space phasor combinations for active vectors and zero
vectors used in the present work (for sequence-1)
120
S
15
35
51
53
13
A -phase
axis
G
H
I
J
K
L
M
N
P
Q
R
axis o
|
31
O
1
2
3
4
5
6
11
33 55
55
11
33
o
sr
V
( ) 2 V 3
dc
The reference space phasor Vsr for the dual inverter
121
Experimental results : lower speed range
Pole voltage and its FFT Phase voltage and its FFT
122
Experimental results : higher speed range
Pole voltage and its FFT Phase voltage and its FFT
123
Three-level inverter configuration with common mode
124
A three level inverter scheme based on open-
end winding configuration is proposed, which,
uses only half the DC link voltage, compared to
the scheme based on conventional NPC inverter
The proposed scheme generates the three-level
voltage waveforms across the motor phases with
Zero common mode voltage in the motor phase voltage
Zero common mode voltage in the pole voltage

Three-level inverter configuration with common mode
voltage elimination
125
The five-level inverter configuration
126
B axis
C axis
A axis
-+- 0+- ++-
+0-
+--
00-
++0
-0-
0+0
0--
+00
0-0
+0+
--0
00+
-00
0++
-+0
-++
-0+
--+
0-+ +-+
+-0
+++
000
---
V
dc
/2
K J
I
H
G
B
C
A
F E
D
L
M
N
O P Q
R
0
axis o
axis |
space vector combinations for inverter-A , inverter-B
127
1
A-phase Axis
B-phase Axis
C-phase Axis
axis o
axis |
2
3 4
5
6 7
8
9
10
11 12
13
14
15
17 18
19
20
21
22
23 24 25 26
27
28
29
30
31
32
16
33 34 35
36
37
38
39
40
41
42 43 44 45 46
47
48
49
50
51
52
53
54
55
56 57 58
59
60
61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
81
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
V
dc

Five-level Inverter voltage space vector representation
Shaded inverter voltage space
phasor locations produce zero
common mode voltage in the
phase voltage of IM
128
B-phase
Axis
C-phase Axis
axis o
axis |
V
dc

A- phase
axis
0
A
B
C
D
E
F
R
H J
L
N P
G
I
K
M
O
Q
Inverter voltage space phasor locations with zero common
mode voltage in the phase voltage of IM
130
o
|
V
cm

0
12
dc
V
12
dc
V
V
cm1
Group E
Group C
Group D
Voltage space vectors of inverter-A (belonging to group C, D
and E) in a three dimensional plane: --0 plane
131
The resultant three-level space vector configuration when group D switching
states are used to switch inverters-A and inverter-B
132
Inverter configuration with common mode voltage elimination
133
elimination
A three-level inverter configuration with common mode elimination
is proposed for an induction motor drive with open-end windings.
Common mode voltage generated across the motor phases is zero.
Suppresses the common mode currents which otherwise will flow
in the machine windings.
Common mode voltage in the inverter pole voltage is zero.
The problems associated with the common mode voltages inducing
currents in the leakage capacitances are completely eliminated (as
the electrostatic coupling between stator winding to stator iron and
between stator winding and rotor iron is ineffective)
Only two power supplies are required whereas the equivalent
three-level inverter configuration with common mode elimination
based on H-bridge topology requires six isolated power supplies.
DC link voltage requirement is only half to that of the conventional
three-level inverter configuration with common mode elimination.

Salient Features
134
B-phase
Axis
C-phase
Axis
axis o
axis |
1
V
dc

A phase
axis
+0- , 000
000 , 0-+
-+0 , 000
000 , +0-
0-+ , 000
000, -+0
0+- , -0+
-0+, +-0
+-0 , 0+-
+0- , -0+
0+- , 0-+
-+0 , +-0
-0+ , +0-
+-0,-0+
0+-,+-0
-0+ , 0+-
+-0 , -+0
0-+ , 0+-
000, 000
Output vectors selected for inverter switching
135
Pole voltage waveforms for modulation index 0.4
(Layer 1 operation) and its FFT
136
Phase-A voltage and phase-A current waveform for
modulation index 0.4 and FFT of phase voltage (Layer 1)
137
(Layer 2 operation) and its FFT
138
modulation index 0.7 and FFT of phase voltage (Layer 2)
139
(over-modulation operation) and its FFT
140
modulation index 0.95 and FFT of phase voltage
141
Pole voltage waveforms for twelve-step mode and its
FFT
142
twelve-step mode and FFT of phase voltage
143
Five-level inverter configuration with common mode
144
Power Scheme of One Leg of Proposed Five-level Inverter by
Cascading Conventional Two-level and Three-level VSIs
Leve
l
Pole
Voltag
e
State of the switch*
S
11
S
21
S
24
S
41
2 V
dc
/4 1 1 0 1
1 V
dc
/8 0 1 0 1
0 0 0 0 0 1
-1 -V
dc
/8 0 0 1 1
-2 -V
dc
/4 0 0 1 0
*[1 ON, 0 OFF]
S
11
-S
14
, S
21
-S
34
, S
24
-S
31
, and S
41
-S
44
are
complementary pairs of switches
IGBT Gating Logic
145
Power Schematic for The Nine-level Inverter Configuration
146
Switching States and Voltage Space Vector Locations of Inverter-
A (a Five-level Inverter)
96 Sectors
61 Vectors
125 Switching States
147
Groups of Common-mode Voltage Generated by Individual Five-level Inverter
Group Switching state of five-level inverter V
CM
1 222 V
dc
/4
2 122, 212, 221 5V
dc
/24
3 022, 112, 121, 202, 211, 220 V
dc
/6
4 012, 021, 102, 111, 120, 201, 210, 22-1, 2-12, -122 V
dc
/8
5 002, 011, 020, 101, 110, 12-1, 1-12, 200, 21-1, 22-2, 2-11, 2-22, -112, -121, -
222
V
dc
/12
6 001, 010, 02-1, 0-12, 100, 11-1, 12-2, 1-11, 1-22, 20-1, 21-2, 2-10, 2-21, -
102, -111, -120, -212, -221
V
dc
/24
7 000, 01-1, 02-2, 0-11, 0-22, 10-1, 11-2, 1-10, 1-21, 20-2, 2-1-1, 2-20, -101, -
110, -12-1, -1-12, -202, -211, -220
0
8 00-1, 01-2, 0-10, 0-21, 10-2, 1-1-1, 1-20, 2-1-2, 2-2-1, -100, -11-1, -12-2, -
1-11, -1-22, -201, -210, -22-1, -2-12
-V
dc
/24
9 00-2, 0-1-1, 0-20, 1-1-2, 1-2-1, 2-2-2, -10-1, -11-2, -1-10, -1-21, -200, -21-1, -
22-2, -2-11, -2-22,
-V
dc
/12
10 0-1-2, 0-2-1, 1-2-2, -10-2, -1-1-1, -1-20, -20-1, -21-2, -2-10, -2-21 -V
dc
/8
11 0-2-2, -1-1-2, -1-2-1, -20-2, -2-1-1, -2-20 -V
dc
/6
12 -1-2-2, -2-1-2, -2-2-1 -5V
dc
/24
13 -2-2-2 -V
dc
/4
148
Groups of Switching States and Amplitude of Resulting Common-mode
Voltage in Five-level Inverter (Inverter-A and Inverter-A)
149
Voltage Vector With Corresponding Switching State Resulting Zero Common-
mode Voltage in Five-level Inverter (Inv.-A and Inv.-A)
24 Sectors
19 Vectors
19 Switching States
150
Combined Voltage Space Vector Locations of a Dual Five-level Inverter Fed
Open-end Winding IM Drive (a Nine-level Inverter)
384 Sectors
217 Vectors
15,625 Switching States
151
Number of Redundant Switching States Available for Voltage
Vectors of Five-level Inverter with Zero Common-mode Voltage
96 Sectors
61 Vectors
361 Switching States
152
Switching State Combination Selected to Generate The Voltage
Space Phasors of Five-level Inverter With Zero CMV
96 Sectors
61 Vectors
61 Switching States
153
Power Scheme of Proposed Five-level Inverter With CME
Two-level
operation
m=0.2
Pole voltage spectrum Phase voltage spectrum
Three-level
operation
m=0.33
Four-level
operation
m=0.6
Five-level
operation
m=0.72
Over
modulation
m=0.97
Four-level
operation
m=0.6
Five-level operation m= 0.72 Over modulation m = 0.97
160
Three-level inverter scheme with common mode
voltage elimination and dc-link capacitor
voltage balancing for an open end
winding induction motor drive

161
Power schematic of a three-level inverter with common-mode voltage elimination
The proposed scheme generates the three-level voltage waveforms across the
motor phases with
Zero common mode voltage in the motor phase voltage
Zero common mode voltage in the pole voltage

Each side on motor is fed
with three-level inverters
Requires half the DC link
voltage, compared to the
scheme based on conventional
NPC inverter
162
Multiplicity of inverter vector locations has been effectively utilized
to arrive at a DC Link capacitor voltage-balancing scheme

The proposed capacitor voltage-balancing scheme is implemented
without compromising on the SVPWM scheme and a simple
hysteresis controller can be used to balance the DC link capacitor
voltages

Requires only one isolated passive front-end power supply

Salient Features
Three-level inverter with common-mode voltage elimination
163
The switching combinations for three-level inverter with common
mode voltage elimination
Proposed scheme generates the three-
level voltage waveforms across the motor
phases with
Zero common mode voltage in the
motor phase voltage
Zero common mode voltage in the
pole voltage
The DC Link voltage is half as compared
to the three-level NPC inverter
Switching combination +0-, -0+ means inverter-A
state is +0- inverter-B state is -0+
164
Inverter-induction motor system model
Each leg of individual three-level inverter is modeled
as a three pole switch
1 => - V
dc
/2
2 => 0
3 => + V
dc
/2
Switching function

S = 1 if switch is connected to -V
dc
/2
2 if switch is connected to 0
3 if switch is connected to Vdc/2

165
Inverter-induction motor system model
Source current i
S
Currents drawn from DC link- i
1
, i
2
, i
3
Inverter-A currents -i
1A
,i
2A
,i
3A
, Inverter-A currents -i
1B
,i
2B
,i
3B
Induction motor currents- i
a
, i
b
, i
c
166
The inverter pole voltages with respect to negative DC rail, in terms of capacitor
voltages
Analysis of DC link capacitor voltage unbalance for proposed three-
level inverter configuration
167
The currents drawn from the DC Link nodes (i
1
,i
2
,i
3
) in terms of motor currents (i
a
, i
b
, i
c
)
Inverter-A:
Inverter-B:
Motor
currents
Motor currents
168
The current drawn from the middle point on the DC link
is responsible for unbalance
169
1
SV
SV
SV
SV
SV
SV
MV
MV
MV
LV
LV
LV
LV
MV
MV
ZV
MV
LV
LV
LV: Large Voltage Vectors
ZV: Zero Voltage Vectors
SV: Small Voltage vectors
MV: Medium Voltage vectors
Classification of the inverter voltage vectors
Classification is based on
Voltage produced in the output
Connection of IM phase winding
to the Capacitors
170
G (+0-, -0+)
C2
C1
A C
B
Large Voltage Vectors (LV) and their effect on DC link
capacitor voltages
Two windings directly across full
DC link
One winding short circuited at
middle DC link point
No effect on capacitor voltages as
load current is drawn directly from
source
171
C2
C1
+0- , 0-+
C
B
A
(b)
C2
C1
0+- , -0+
C
A
B
(a)
Middle Voltage Vectors (MV) and their effect on DC
link capacitor voltages
One winding directly across full DC link
One windings across each capacitor
The difference between these two
winding currents is drawn through the
mid-point of DC link
Has unbalancing effect on capacitor
voltages
Each MV vector location has two switching combinations
The IM phase windings are connected to opposite capacitors in these two
combinations
Ex: vector location H
(a) 0+-,-0+ A phase bottom capacitor and B phase top capacitor
(b) 0+-,-0+ A phase top capacitor and B phase bottom capacitor
172
C2
C1
(a) 000,-0+
A
C
B
C2
C1
(b) +0-, 000
C
A
B
C2
C1
(c) +-0 , 0-+
A
C
B
C2
C1
(d) 0+- , -+0
A
C
B
Space vector combinations and their effect on DC link capacitor voltages
inverter vector location A (Small Voltage vector)
One winding
across each
capacitor
One winding
across each
capacitor
Two windings
across TOP
capacitor
Two windings
across BOTTOM
capacitor
NSV NSV
LSV
USV
Normal Small
Voltage Vector
Normal Small
Voltage Vector
Lower Small
Voltage Vector
Upper Small
Voltage Vector
173
+-0 , 0-+
000 , -0+
+0- , 000
0+- , -+0
-+0 , -0+
0+- , 000
000 , 0-+
+0- , +-0
0+- , +0-
000 , +-0
-+0 , 000
-0+ , 0-+
0-+ , +-0
-0+ , 000
000 , +0-
-+0 , 0+-
-0+ , -+0
000 , 0+-
0-+ , 000
+-0 , +0-
+0- , 0+-
+-0 , 000
000,-+0
0-+ , -0+
0+- , -0+
+0- , 0-+
-0+, +-0
-+0 , +0-
+-0 , 0+-
0-+ , -+0
+0- , -0+
0+- , 0-+
-+0 , +-0
-0+ , +0-
+-0,-0+
+0-,-+0
-+0 , 0-+
0+-,+-0
-0+ , 0+-
0-+ , +0-
+-0 , -+0
0-+ , 0+-
0
LV: Large Voltage Vectors
ZV: Zero Voltage Vectors
MV: Medium Voltage vectors
USV: Upper Small Voltage vectors
NSV: Normal Small Voltage vectors
LSV: Lower Small Voltage vectors

Summary: Classification of switching combinations of proposed inverter
voltage vector locations
174
Thus inverter voltage vectors belonging to ZV, NSV, MV and LV can be used effectively
to maintain the voltage balance across the DC Link capacitors
No voltage/current feedback required
Works on alternate switching of NSV and MV switching combinations
DC link capacitor voltage balancing scheme for the
proposed three-level inverter fed induction motor drive
ZV and LV do not have any unbalancing
effect on the DC link capacitor voltages
MV and NSV group generate very low
voltage unbalance. Each have two switching
combinations with phase windings
EXCHANGING their connections to DC
link capacitors.
Thus, effect of one switching combination
on the capacitor voltages is nullified by
another switching combination
Alternate switching of NSV and MV
switching combinations in consecutive
sampling durations will maintain the
capacitor voltages balanced.
000 , -0+
+0- , 000
0+- , 000
000 , 0-+
000 , +-0
-+0 , 000
-0+ , 000
000 , +0-
000 , 0+-
0-+ , 000
+-0 , 000
000,-+0
0+- , -0+
+0- , 0-+
-0+, +-0
-+0 , +0-
+-0 , 0+-
0-+ , -+0
+0- , -0+
0+- , 0-+
-+0 , +-0
-0+ , +0-
+-0,-0+
+0-,-+0
-+0 , 0-+
0+-,+-0
-0+ , 0+-
0-+ , +0-
+-0 , -+0
0-+ , 0+-
0
175
POS_SEQ
NEG_SEQ
A G R A G A R A
+0-, -+0 000, -0+ +0-, 000 000, -0+ +0-, 000 +0-, -0+ +0-, -0+
T
S
2*T
S
+-0, -0+
(a) Sector formed by inverter vectors A-G-R
0 A B 0 A 0 B 0
0+- , 000 000, 000 000, 000
000, -0+
000,000
000, 0-+
000, 000 +0-, 000
(b) Sector formed by inverter vectors 0-A-B
(c) SEQ signal
high

low

T
S
T
S
The sequence of various switching combinations during
POS_SEQ and NEG_SEQ
176
POS_SEQ
NEG_SEQ
A G R A G A R A
+0-, -+0 000, -0+ +0-, 000 000, -0+ +0-, 000 +0-, -0+ +0-, -0+
T
S
2*T
S
+-0, -0+
Sector formed by inverter voltage vectors A-G-R
high

low

T
S
T
S
A
B
H
Y
G
Alternate switching combinations are selected for A
(NSV) and R(MV) inverter voltage vectors in the
consecutive sampling interval
The capacitor voltage unbalance in sampling interval
POS_SEQ is nullified in next sampling interval
NEG_SEQ
177
POS_SEQ
NEG_SEQ
T
S
2*T
S
high

low

A
B
H
Y
G
0 A B 0 A 0 B 0
0+- , 000 000, 000 000, 000
000, -0+
000,000
000, 0-+
000, 000 +0-, 000
Sector formed by inverter voltage vectors 0-A-B
T
S
T
S
Alternate switching combinations are selected for A
(NSV) and B(NSV) inverter voltage vectors in the
consecutive sampling interval
The capacitor voltage unbalance in sampling interval
POS_SEQ is nullified in next sampling interval
NEG_SEQ
178
SVPWM
modulator
SEQ
Switching
Combination
Selector
Gate signal
decoding
Gate
signals
State
DSP PAL
Open loop DC Link capacitor voltage balancing scheme
179
Open loop DC Link capacitor voltage balancing controller (Simulation results)
DC Link
Voltage
Capacitor
voltages
180
Deviation in the capacitor voltages when the open loop DC Link balancing
controller is turned off (Simulation results).
DC Link
Voltage
Capacitor
voltages
181
Harmonic frequency distribution of phase voltages for balanced and
unbalanced capacitor voltage conditions
Low order even harmonics causes damaging effects to the machine because of the
current harmonics resulting in torque pulsations and increased machine losses
182
sec
Disadvantage: Gradual drift in the capacitor voltages in the open loop scheme
Possible Reasons:
Use of the asynchronous PWM,
Unequal time durations of the MV and NSV inverter vectors in
consecutive switching intervals
Unbalanced load currents etc
Open loop DC Link capacitor voltage balancing scheme
183
Hysteresis
Controller
0
/ O P
v
C2
v
C1
c
V A
1
0
H
P
L
P
L
N
H
N
1
/ O P
Control Band
Av
C
Hysteresis controller based closed loop DC Link balancing scheme
Switching combinations from USV charge
lower capacitor and discharge upper
capacitor
Switching combinations from LSV
discharge lower capacitor and charge upper
capacitor
USV and LSV group switching
combinations are used to balance the
capacitor voltages
Hysteresis controller selects the LSV or
USV group instead of NSV depending
upon the difference in the capacitor
voltages, Av
C
Closed loop scheme involves sensing
the capacitor voltages
184
Inverter
Switching
Vector
Location
Switching
Combination
Selector
Inverter
gate signals
decoding
Hysteresis
Controller
SEQ
State
/ O P
v
C2
v
C1
0
DSP
PWM
Algorithm
Inverter
A
Inverter
B
Induction
motor
Inverter
A
Inverter
B
PAL
Hysteresis controller based closed loop DC Link balancing scheme
185
Operation of closed loop controller for DC link balancing (Simulation results)
Capacitor
voltages
Av
C
Controller
output state
186
The deviation in the capacitor voltages when the DC Link voltage-balancing
scheme is turned off for a small interval
187
DC Link voltage-balancing scheme in 12-step mode
SV are not switched for longer duration in the 12-step mode
Capacitor voltages deviate from the balanced state
188
DC Link voltage-balancing scheme in 12-step mode
Slight reduction in the modulation index restores the capacitor voltages to
balanced state in 12-step mode
189
Experimental Results
190
Balancing of DC link capacitor voltages V
C1
and V
C2
during steady state
operation
V
C1,
V
C2
191
Balancing of the DC Link capacitor voltages after the controller is disabled
for small interval, inner layer operation
V
C1
V
C2
192
Balancing of the DC Link capacitor voltages after the controller is disabled
for small interval, outer layer operation
V
C1
V
C2
193
The DC link voltages and machine phase current under while machine operating
in inner layer is accelerated to outer-layer and then to over-modulation
V
C1,
V
C2
Phase
current

194
The DC link voltages and machine phase current under while machine
operating in inner layer is subjected to speed reversal
V
C1,
V
C2
Phase
current

195
Space vector PWM signal generation for multi-level
inverters using only the sampled amplitudes of
reference phase voltages

196
Conventional Space Vector Based PWM
1. Identify the sector
2. Determine the timings
3. Determine the Actual vectors
4. Generate the Gate signals
Sector Identification
a. With Angle and magnitude information
b. Using level comparators
Timing
a. Direct equations
b. Mapping the sector to an appropriate inner sector
Space vector PWM signal generation for multi-level inverters
using only the sampled amplitudes of reference phase voltages
197
In the Proposed Work
1. Sector identification is not required
2. No need to compute switching times for each vector
3. Does not use look-up tables to select vectors
4. The inverter leg switching times are directly obtained with a simple
algorithm using only the sampled amplitudes of the reference
phase voltages
Faster computations
Generate the inverter gate signals for the entire
modulation range extending up to six step mode

Space vector PWM signal generation for multi-level inverters
using only the sampled amplitudes of reference phase voltages
198
Two level SVPWM
199
( )
1 max min
/ 2
offset
V V V = +
max , ,
is maximum of
A B C
V V V V
min , ,
is minimum of
A B C
V V V V
Addition of V
offset1
centers the active inverter vectors in the switching
interval for two-level inverters but not for multilevel inverters
The max phase may not determine the third cross, min phase
may not determine the first cross
Correct determination of the phases which determines the first
-cross,second-cross and third-cross is required for multilevel inverters
Offset voltage determination for Two level SVPWM
200
Reference voltages and triangular carriers for a five-level SPWM

Power Converters and Drives Lab - A Research Overview

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CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

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