Layout design rules:

For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. They act as interface between the circuit designer and the process engineer.

The fundamental unity in the definition of a set of design rules is the minimum line width.

i.e. a design rule stands for the minimum mask dimension that can be safely transferred the semiconductor material. Even for the same minimum dimension, design rules differ from company to company and from process to process.
However, there are CAD tools that allow the migration of the design between compatible process.

For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. They act as interface between the circuit designer and the process engineer.

Design Rules:
N- Well
r101 r102 r110 Minimum width Between wells Minimum well Area 12 12 144 2

r 101

r 102

NWell

r201

Minimum N+ and P+ diffusion width

r 201

P+ Diff

NWell

r 201

N+ Diff

r202

Between two P+ and N+ diffusions

r 202

P+ Diff

NWell

r 202

N+ Diff

r203

Extra N-well after P+ diffusion

r 203 P+ Diff

r 203
NWell

N+ Diff

r204

Between N+ diffusion and n-well

P+ Diff

NWell r 204

N+ Diff

r210

Minimum diffusion area

162

r 210

P+ Diff

NWell

r 210

N+ Diff

r301

Polysilicon Width

Polysilicon r 301

P+ Diff

NWell Polysilicon r 301

N+ Diff

r302

Polysilicon gate on Diffusion

Polysilicon

r 302 P+ Diff

NWell Polysilicon

r 302 N+ Diff

r307

Extra Polysilicon surrounding Diffusion

Polysilicon r 307

P+ Diff r 307 NWell Polysilicon r 307

N+ Diff r 307

r304

Between two Polysilicon boxes

Polysilicon

r 304 P+ Diff

NWell Polysilicon

r 304 N+ Diff

r307

Diffusion after Polysilicon

Polysilicon

r 307

r 307
P+ Diff

NWell Polysilicon

r 307

r 307 N+ Diff

r401

Contact width 2

Contact r 401

Polysilicon Contact

Metal/Polysilicon Contact

r404

Extra Poly surrounding contact

Contact

r 404 Polysilicon Contact

r 404

Metal/Polysilicon Contact

r405

Extra metal surrounding contact

Contact

Polysilicon Contact

Metal/Polysilicon Contact

r 405

r 405

r403

Extra diffusion surrounding contact 1

Polysilicon r 403

P+ Diff

NWell r 403 Polysilicon

N+ Diff

r501

Between two Metals 4

Metal 1
r 501

Metal 4

Metal 2 r 501 Metal 3

Metal 5

Metal 6

r510

Minimum Metal area 162

Metal 1
r 510 r 510

Metal 4

Metal 2 r 510 r 510

Metal 5

Metal 3 r 510 r 510

Metal 6

GATE EXTENSION:

Poly does not cross diffusion Creating a short circuit

It is necessary for the poly to completely cross active, other wise the transistor that has been created crossing of diffusion and poly, will be shorted by diffused path of source and drain.

2 Poly crosses diffusion

Proper Transistor Formed

Diffused Path Between Source And Drain

NAND2 layout

NOR2 layout

Constructing a minimum area layout

Stick diagram layout of the complex CMOS logic gate with arbitrary ordering of poly gate columns.

Ordering of polysilicon gate columns in Euler graph sequence results in uninterrupted p-type and n-type diffusion areas. Adv: Compact area, simple routing of signals and less parasitic capacitance.

2 I/P MUX AND ITS LAYOUT F = (A.S+B.S)

4 input NAND gate:

STICK DIAGRAMS

CONCEPT
Popular Way Of symbolic design. Free hand layout

Colored lines for various process layers.

Poly crossing diffusion gives transistors. Metal touching diffusion gives contacts.

 Notation gives only relative position of various design components. A compactor is used to convert it into absolute design.

Concept

The compactor translates design rules into constraints on the component positions. It also gives optimized design layout with efforts for minimization of area and cost function.

Pros and cons

Designer does not have to worry about design rules. Compactor takes care of that.

Outcome of the compactor may be unpredictable and may not match manual approach.

Typical Stick Diagram

Layers in the stick diagrams

The Procedure For Drawing Stick Diagrams:

Draw stick diagrams for the above circuits.

Back end optimization of a circuit

using Euler's Graph approach

Constructing a minimum area layout

Stick diagram layout of the complex CMOS logic gate with arbitrary ordering of poly gate columns.

Ordering of polysilicon gate columns in Euler graph sequence results in uninterrupted p-type and n-type diffusion areas. Adv: Compact area, simple routing of signals and less parasitic capacitance.

Euler Graph Approach:

(Good Density, Min Area, Abutting of S-D Connections, Single Diffusion Strip In Both Wells, , Easy Automation) Construction Of Logic Graph: 1. Vertices : Nodes of the N/W. 2. Edge: I/P. 3. Dual Graphs for PUN & PDN. Identification Of Euler Paths: 1. Path through all nodes such that an edge is visited only once. 2. Uninterrupted diffusion strip in the layout is possible iff Euler path exists. 3. Many solutions exist. 4. Common Euler path in PUN & PDN 5. Sequence of edges in the Euler path = Order of I/Ps in the layout.

E-D-A-B-C

Ex: 1.

Ex: 2.

Ex: 3.
Effect Of Restructuring

Ex: 3. Effect Of Restructuring

Ex: 3. Effect Of Restructuring

Sketch a stick diagram for a combinational circuit evaluating following Boolean expression.