UNIT V

INTRODUCTION TO VERILOG
 TOPICS TO BE COVERED

• Lexical conventions
• Data types
• Modules and ports
• Gate level modeling
 Lexical conventions

• Whitespace (blank space, tab, new line)

• Comment statements
// - for one line comment
/* */ - for multiple line comment
• Operators (unary, binary, ternary)
• Number specification (sized & unsized)
• Identifiers
• Data types (integer, real, time)
• Verilog supports four major levels of
abstraction
2. Behavioral level
3. Dataflow level
4. Gate level
5. Switch level

• All 4 levels can be mixed and used in any

design using verilog.
 Module
• Module is a basic building block in verilog
• Module provides necessary functionality to
higher level blocks but hides the internal
implementation.
• Keyword – module followed by endmodule
Syntax:
module <module name> (list of ports)
……functionality…..

endmodule
Components of a module
• Verilog allows multiple modules to be defined
in a single file.
• Modules can be defined in any order in the
file.
Example – SR latch
 Verilog Code

// module name and port list

module srlatch (Q,Qbar,Sbar,Rbar);

// port declarations
output Q,Qbar;
input Sbar,Rbar;
 Verilog Code…

// Instantiate low level modules

nand n1 (Q, Sbar, Qbar);
nand n2 (Qbar, Rbar, Q);

//endmodule statement
endmodule
• All parts except module, module name and
endmodule are optional.
 Ports

• provide interface such that the module

communicates with the external world.
• ports are also referred as terminals.
• ports are always declared as wires or
registers depending on their type
Port Declarations
Port Connection Rules
 Port Connection Rules…

Port type Internal External

type type

Input net Reg or net

Ouput Reg or net net

Inout net net

 Port Connection Rules..

• Different sized ports can be connected but a

warning is issued indicating - widths do not
match.

• Unconnected ports can also be used

Eg. fulladd4 fa(sum, , a,b,cin);

• Ports can be connected to signals either by

ordered list or by names.
Gate Level Modeling
Multiplexer (4 to 1)
 Verilog Code
//module name and port list
module mux4to1 (out,i0,i1,i2,i3,sel1,sel0);

// Port declarations
output out;
input i0,i1,i2,i3;
input sel1,sel0;

//Internal wire declarations

wire s1n,s0n;
wire y0,y1,y2,y3;

// Gate instantiations
not (s1n,sel1);
not (s0n,sel0);
// and gate instantiations
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,sel0);
and (y2,i2,sel1,s0n);
and (y3,i3,sel1,sel0);

// or gate instantiation
or (out,y0,y1,y2,y3);

endmodule
Stimulus or Test Bench for MUX
 Stimulus code for MUX
//stimulus module
module stimulus;

// variable declaration connected to inputs

reg IN0, IN1, IN2, IN3;
reg S1, S0;

// declare output wire

wire Z;

// instantiate the component to be tested

mux4to1 testmux (Z, IN0, IN1, IN2, IN3, S1, S0);
// Define stimulus
initial

begin
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
$display(“IN0 = %b, IN1 = %b, IN2 = %b, IN3 = %b\n”, IN0, IN1, IN2, IN3);

S1 = 0; S0 = 0;
$display(“S1 = %b, S0 = %b,Z = %b\n”, S1, S0,Z);

S1 = 0; S0 = 1;
$display(“S1 = %b, S0 = %b,Z = %b\n”, S1, S0,Z);

S1 = 1; S0 = 0;
$display(“S1 = %b, S0 = %b,Z = %b\n”, S1, S0,Z);

S1 = 1; S0 = 1;
$display(“S1 = %b, S0 = %b,Z = %b\n”, S1, S0,Z);
end

endmodule