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# Department of Technical Education

Name : P. Srinivasa Rao
Designation : Lecturer
Branch : Electronics & Communication Engg.
Year/Semester : III semester
Subject : Digital Electronics
Subject code : CM-305
Topic : Counters & Registers
Duration : 50mts
Sub topic : UP/DOWN counter
Teaching Aids : PPT Diagrams
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OBJECTIVES

to

## • Draw the timing diagram of Up-down counter.

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Recollection
1. What is up counter?
It is the counter which is capable of progressing in the
forward direction, through a certain counting sequence.

## Ex: A 2-bit binary counter with a upward counting

sequence of 0,1,2,3.

## 2. What is down counter?

It is the counter which is capable of progressing in the
reverse direction, through a certain counting sequence.

## Ex: A 2-bit binary counter with a downward counting

sequence of 3,2,1,0.
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3 . What is meant by Edge triggering?
It means that the flip flop is changing the state either
at the positive edge (raising edge) or at the negative
edge (falling edge) of the clock pulse.

## 4. Draw the clock pulse showing positive & negative

edge triggered type.

## Rising Falling edge

edge

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UP/DOWN SEQUENCE FOR A 3-BIT BINARY
COUNTER

Clock UP QC QB QA DOWN
pulse
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1CM305.531 1 6
Principle of 3-bit UP/DOWN counter

## • UP/DOWN is a control input which determines the

basic operation of the counter.

be performed .

to be performed.

## • The out put of the counter is given by Q= QC QB QA

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• In this counter flip flop in the lower order position is
complemented with every clock pulse .

## • From the truth table notice that QA changes for every

clock pulse for both UP/DOWN sequences.

## • First flip flop toggles on each clock pulse because of J

&K inputs are at HIGH .

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UP MODE OF OPERATION

pulse.

## • At the second clock pulse QA=0 & QB=1.

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• The output of Qc changes its state on the next
clock pulse when QA=QB=1.

## • When the fourth clock pulse occurs Qc changes its

state from 0 to 1.

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CONDITIONS FOR UP MODE OF OPERATION:

condition
JB=KB=QA.UP.

## • Similarly the inputs of the third flip flop must be equal to 1

under the condition
JC=KC=QA.QB.UP.

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DOWN MODE OF OPERATION:

when QA=0.

QA=QB=0.

## The above two changes can be observed from the truth

table.

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CONDITIONS FOR DOWN MODE OF OPERATION

the condition
JB=KB=QA.DOWN

## the condition JC=KC=QA.QB.DOWN

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TIMING DIAGRAM

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Note from the Timing diagram

triggered.

## • Up operation is performed upto the trailing edge of the

forth clock pulse .

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SUMMARY

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QUIZ

## 1. The counter which is capable of progressing in the

forward direction is called

a) up counter

b) Down counter

d) ripple counter

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1. Preset and clear inputs are called

d) synchronous inputs

f) asynchronous inputs

c) control inputs

d) timing inputs

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3. In the case of up operation Up / Down pin becomes

a) 0

b) 1

c) High

d) both b & c

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4. In Mod-16 up counter the no. of flip-flops are

a) 1

b) 2

h) 3

j) 4

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Questions

## 5. Is the up/ down counter can be classified as

synchronous counter of asynchronous counter?

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