DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH

NAME : K.SRI LAKSHMI

DESIGNATION : LECTURER
BRANCH : ELECTRONICS AND
COMMUNICATION ENG.
INSTITUTE : G.P.W.KAKINADA, E.G.DT.
SEMESTER : III SEMESTER
SUBJECT : DIGITAL ELECTRONICS
SUBJECT CODE : CM-305
TOPIC : FLIP FLOPS
DURATION : 100 min
SUB TOPIC : MASTER-SLAVE FLIP FLOP, Flip- Flop.
Ics
TEACHING AIDS : DIAGRAM,TRUTH TABLE
CM305.38 1
OBJECTIVES

• On completion of this topic you would be able to know

• the elimination of race condition, working of master

slave J-K flip flop .

• The different TTL technology and CMOS technology

Flip-flop IC chips

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Recap

• Define Flip Flop

• Mention the types of Flip flops

• Draw backs of JK flip flop

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J-K MASTER SLAVE FLIP- FLOP

• A master slave flip flop is a combination of two

clocked flip flops , the first is called the master and
second is called slave.

• Master is positively clocked and slave is

negatively clocked.

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 On summarizing the working of J-K master slave
flip flop,

4. While the clock is high ,the master is active ,and

the slave is inactive.

7. While the clock is low , the master is inactive and

the slave is active.

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 S
J
Q
clk
MASTER SLAVE

Q
K R
R
RR

FIG(1) MASTER-SLAVE FLIP-FLOP

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• In a master slave J-K flip flop assume low Q and
high Q for an input clock high , the master goes in
to the set state producing high ‘S’ and low ‘R’.

• No change in Q and Q output . As the slave in

inactive while the clock is high.

• When clock goes low, the high ‘S’ and low ‘R’
forces the slave in to the set state producing a
high Q and low Q.

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• There are two distinct steps in setting the final
Q output .
• The Master is set while the clock is high.
• The slave is set while the clock is low.
• The truth table below in fig(2) ,shows that when
clock is high & J=1, K=0 the flip flop set.
• When clock is high , and J=0,K=1.the flip flop reset.
• When clock is high and J=K=0, no change .
• when clock is high J=K=1,then the flip flop toggles.

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TRUTH TABLE OF J-K MASTER FLIP FLOP

INPUTS OUTPUTS
COMMENT
CLK J K Q(n+1)
NO CHANGE
X 0 0 Qn

1 RESET
0 0
1 SET
1 0
Qn TOGGLE
1 11

FIG(2) truth table of master-slave flip-flop

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IC NUMBER FUNCTION

7473 Dual j-k Flip Flop

7474 Dual D Flip Flop

7475 Quad Bi-stable latch

7476 Dual j-k Flip Flop

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IC NUMBER FUNCTION
74107 Dual j-k Flip Flop

74109 Dual j-k Flip Flop

74174 Hex D Flip Flop

74173 Quad D Flip Flop

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Summary

We discussed about

• Race around condition

• Working of master slave J-K Flip flop.

• Flip Flop Ics

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Quiz

Master –slave JK Flip flop is

a cascade connection of two clocked Flip flops.

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Questions

1. How do you eliminate the race condition?

3. What is the advantage of master slave flip flop?

3. What is the state called when J and K are high

along with clock in master slave J-K flip flop?

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