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ANDHRA PRADESH
Name : M. Hemalatha
Designation : Lecturer
Branch : ECE
Institute : G.M.R.P., Madanapalle
Semester : III Semester
Subject : Digital Electronics
Subject Code : EC – 304
Topic : Sequential logic circuits
Duration : 100 Mts.
Sub-Topic : Modulo-n, modulo-3, Mod-10
counter
Teaching Aids : PPT, Diagrams
EC304.42 to 43 1
OBJECTIVES
EC304.42 to 43 2
Modulo-n counter(Divide-N counter)
EC304.42 to 43 3
MOD-3 COUNTER
EC304.42 to 43 4
Mod-3 counter is as shown in the figure
EC304.42 to 43 5
This counter has to reset to 0 when the output reads 11.
When the third clock pulse occurs, NAND gate gets the
two inputs QA and QB as HIGH, hence Output of NAND
gate LOW, which resets all the FlipFlops.
EC304.42 to 43 6
MOD-3 COUNTER TIMING DIAGRAM
EC304.42 to 43 7
Mod-10 ripple counter(Decade counter)
EC304.42 to 43 8
Decade counter
EC304.42 to 43 9
Q1 and Q3 are connected to the NAND gate inputs.
EC304.42 to 43 10
Timing diagrams of decade counter
EC304.42 to 43 11
SUMMARY
Divide-n counter
Mod-3 counter
EC304.42 to 43 12
Quiz
EC304.42 to 43 13
Quiz
EC304.42 to 43 14
Frequently asked questions
EC304.42 to 43 15