Biswanath Dash Ashutosh Mohanty

Setup and hold concepts Skew and its effects on setup and hold Static timing analysis Dynamic simulation vs STA Tools for STA (Prime time/ Gold time) How prime time works Prime time commands

Setup and Hold time

Setup time is defined as the

minimum amount of time BEFORE the clocks active edge by which the data must be stable for it to be latched correctly

Hold time is defined as the

minimum amount of time AFTER the clocks active edge during which the data must be stable

Flop to Flop Path

Hold Evaluation

Clock Skew

If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be skewed between these flip-flops. clock skew = difference between the times of arrival of clock at the flip-flops Clock skew is due to different delays on different paths from the clock generator to the various flip-flops.
Different length wires (wires have delay) Gates (buffers) on the paths Flip-Flops that clock on different edges (need to invert clock for some flip-flops) Gating the clock to control loading of registers (a very bad idea)

Effect of Skew on Setup

Effect of Skew on Hold

Summary of setup and hold

Setup always calculated from launch edge of FF1 to capture edge of FF2. Hold always calculated from launch of FF1 to launch edge of FF2. If there is a setup violation on your silicon, you can always slow down the clock and still the circuit will work. If there is a hold violation you are in deeeeeeeeeeeeeeeep trouble!!!

Static timing analysis

Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.

Different STA Tools

Synopsys' PrimeTime/PrimeTime-SI STA including delay calculator PrimeTime-SI is doing crosstalk analysis (CCSM) Cadence's CTE(common timing engine) SignalStorm is its delay calculator. (ECSM) Celtic is for noise analysis. (.cdb) Incentia's TimeCraft DO NOT HAVE ITS OWN delay calculator. Mentor graphics SST velocity Extreme DAs Gold time Magmas Quartz Time of

Dynamic Simulation vs STA

DS uses test patterns (vectors) as the i/p to perform timing analysis on only those paths that are activated according to patterns. STA considers all rises and falls in blocks and traces all paths thus allowing verification with a higher degree of accuracy. DS also checks logical functionality of the circuit. STA does not check the logical functionality. STA is faster than DS.

Prime Time/Gold Time

Input file formats
.library format (timing information of a ckt and primitive delay information) .netlist format .delay format (R-C parasitic)

Prime time top level description

How Prime time works ???

Breaking the design into a set of Timing paths Delay calculation - cell delay
- net delay

Constraint checking -setup and hold constraint

-recovery/removal constraints -data-to-data constraints -clock-gating setup/hold constraints -minimum pulse width for clock signals

Prime Time Commands

Report_timing :
Provides general or more information about the timing of the whole design, a group of paths or an individual path. Command options specify the types of paths reported ,scope of design to search for specified paths and type of information included in path reports

Sl no Command
1 2 3 (Without option) -from and -to -delay{max} -delay{min} 4 -nets -capacitance -transition

Description
Reports the single path with the worst setup timing slack in each path group Paths contained in this option will be reported Calculate the setup timesfor all paths Each path is check for hold violations Tells GT to include the nets in the reports Lump capacitance of every net will be reported reports on all the input driving transition on the pin in the path

5
6

-max_paths INT
-nworst INT

the total number(INT) of paths to be reported per group.( default is one)

The number(INT) of enp points to be reported

Sl no
7

Command
-nosplit

Description
Prevent line splitting

-group GROUP_LIST

Select paths in this group

-voltage

Displays the pin supply voltage

10

-input_pins

Displays only the input pins

11

-output_pins

Displays the output pins

Commands

report_clock_timing :
reports the skew,the difference between the longest and shortest clock insertion time, and allow the design to evaluate whether or not the clock tree must be synthesized. A powerful command saves the designer from numerous timing closure spins Eg:

Commands

-report_bottleneck
Reports on the timing bottlenecks in the design When design have a large number of timing violations , bottleneck analysis helps in finding places in design most likely to benefit from design changes(gate resizing or resynthsis under new constarints)

Commands
report_delay_calculation

Generates a detailed report on how GT/PT calculates delay for a specified cell or net timing arc Used for debugging problem