Digital Electronics

Electronics Technology Landon Johnson

Counters

Counter Competencies
29. Given the schematic diagram of a counter circuit, the student will determine if this counter is synchronous or asynchronous. 30. Given a schematic of an asynchronous counter, the student will identify the LSB flip-flop.

31. Given a schematic of a synchronous counter, the student will identify the LSB flip-flop. 32. Given the schematic of a counter and the value currently on the counter, the student will determine the new counter value if an instructor specified number of pulses are applied to the counter

Counter Competencies
33. Given a modulus number from 16 to 32, the student will draw a schematic of flip-flops and NAND gates that will count this modulus starting with zero. 34. Given the schematic diagram of a synchronous counter circuit, the student will determine the modulus of the counter. 35. Given the schematic diagram of a synchronous counter circuit, the student will determine the counting sequence and list the sequence in decimal.

36. Given the schematic diagram of a counter and the clock input frequency, the student will determine the output frequency of the counter.

COUNTER UNIT
Asynchronous up and down counters Asynchronous modulus counters Seven segment displays/ BCD coding Synchronous Counters Pre-settable Counters Ring Counters

COUNTERS CHARACTERISTICS
1. MODULUS- number of counts in one cycle 2. Up or down count

3. Asynchronous or synchronous operation

4. Free running or self stopping

ASYNCHRONOUS COUNTERS
Only LSB flip-flop controlled by the clock input

Also known as a RIPPLE COUNTER

Two or more T flip-flops interconnected, output of each flip-flop connected to clock input of the next. Modulus- number of stable states in each flip-flop cycle Modulus =

N= number of flip-flops

Highest number in count =

N 1

BUILD A 4 BIT RIPPLE COUNTER

1. 4 JK flip-flops in toggle mode- all JK inputs tied high 2. Q outputs connected to clock input of following flip-flop 3. FF A = LSB (one with clock input); toggles when input clock toggles from high to low; FF D = MSB 4. FF B, C, D do not toggle till receive NGT from proceeding FF 5. Direction of count can be reversed by complementing each FFs output or complementing each FFs input
D
D J CLK D K 1 C 1

C
C J CLK K 1 1

B
B J CLK B K 1 1

A
A J CLK A K 1 1

TEST
1. What is the term for the number of counts in one counter cycle? Modulus of the counter 2. How is the modulus determined? 2 N N number of flip flops 3. Since only the first flip-flop of a ripple counter is controlled by a clock, the counter is ____________________? Asynchronous 4. What is the mod number of a counter containing 5 flip-flops? 32 5. What is the highest count of a four bit counter? 31

PROGRAMMING A RIPPLE COUNTER

Counters may be made to recycle after any desired count by using a gate to reset the counter. CONVERT MOD 8 TO MOD6
C
C J CLK C K 1 B 1

B
B J CLK K 1 1

A
A J CLK A K 1 1

INPUT CLK 0 1 2 3 4 5 6 7 C 0 0 0 0 1 1 1 B 0 0 1 1 0 0 1 A 0 1 0 1 0 1 0

B C

master reset

UNSTABLE STATE

3 FLIP FLOPS 2 MOD 8 HIGHEST COUNT 2 1 7

3 3

HOW TO BUILD A COUNTER TO GO FROM ZERO TO MOD NUMBER X

1. Determine smallest number of FFs such that

IF 2 X , SKIP STEPS 2 AND 3

N

2 X
N

2. Connect a NAND gate output to asynchronous clears of all FFs

3. Determine which FFs will be high at count = X Connect the Q outputs of these FFs to NAND gate inputs

BUILD A COUNTER THAT COUNTS FROM ZERO TO NINE (X=MOD 10)

1. Determine smallest number of FFs such that

2 8 and 2 16
3 4

2 X
N

thus 4 FFs are required

2. Connect a NAND gate to asynchronous clears of all FFs 3. Determine which FFs will be high at count = X Connect the Q outputs of these FFs to NAND gate inputs 1 1 0 0
D
D J CLK D K 1 C 1

C
C J CLK K 1 1

B
B J CLK B K 1 1

A
A J CLK A K 1 1

SELF-STOPPING COUNTER
Counters may be made to stop counting after any desired count by using a gate to inhibit the clock. Stop at desired count:

Stop at 1010 1010 2

1
D J CLK D K 1 C 1

0
C J CLK K 1 1

1
B J CLK B K 1 1

0
A J CLK A K 1 1

D C B A

PROGRAMMING COUNTERS USING JK INPUTS

Counters can be controlled using the JK inputs Low on JK of 1st FF will cause it to stop toggling on any count High or low at JK inputs forces counter to skip states

1
D J CLK D K 1 1

1
C J CLK C K 1 1

0
B J CLK B K 1 1

0
A J CLK A K

C D

ASYNCHRONOUS DOWN COUNTER

Direction of count can be reversed by (a) complementing each FFs output or (b) complementing each FFs input

D CLK D

C CLK C

B CLK B

A CLK A

C
C CLK D C CLK

B
B CLK B

A
A CLK A

COUNTER PROBLEM
1. What is the value of the last usable state before the NAND gate resets the circuitry? 11012 1310 2. What value does the NAND gate reset the value to? 1000 2 810 3. What is the modulus of this counter?

4. If count starts at decimal 11 and receives seven clock pulses, what is the new value on the counter? 1210 5. What is the unstable state of the counter? 1110 2 1410
A B C D

0V

S J Q CP K QN R

S J Q CP K QN R

S J Q CP K QN R

S J Q CP K QN R

COUNTER PROBLEM
1. What is the value of the unstable state, in decimal? 1112 710 2. At what value does the NAND gate set the counter to? 0112 310 3. If QA=1, QB=1, and QC=0, and 5 clock pulses are applied: QC= 1 QB= 0 QA= 0 4. What is the modulus of this counter? 4
1 A 2 B 4 C

+V 0V S J Q CP K QN +V R

+V S J Q CP K QN R

+V S J Q CP K QN R

IC ASYNCHRONOUS COUNTERS
Logic Diagram for 7493
___ CPo ___ CP1 MR1 MR2 Qo (LSB) Q1 Q2
*All J, K inputs internally connected HIGH
___ CP1 ___ CPo

J Q CP K QN R

J Q CP K QN R

J Q CP K QN R

J Q CP K QN R

Q3 (MSB)

7493

MR 1 MR 2

Q3

Q2

Q1

Qo

7493 AS A MOD-16 COUNTER

Logic Diagram for 7493
___ CPo ___ CP1 MR1 MR2 Qo (LSB) Q1 Q2
*All J, K inputs internally connected HIGH J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R

Q3 (MSB)

7493
Qo

___ CP1 ___ CPo

Q1

10 kHz

MR 1

MR 2 Q3

Q2

F= 10 kHz/16 = 625 Hz

TEST
Build a MOD 10 counter with a 7493 Logic Diagram for 7493
___ CPo ___ CP1 MR1 MR2 Qo (LSB) Q1 Q2
*All J, K inputs internally connected HIGH J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R

Q3 (MSB)

7493
Qo

___ CP1 ___ CPo

Q1

10 kHz

MR 1

MR 2 Q3

Q2

F= 10 kHz/10 = 1KHz

BCD COUNTER
Binary counter that counts from 0000 to 1001 before it recycles (MOD-10). Widespread applications where pulses or events are to be counted and the results displayed on a decimal numerical read-out. Also used for dividing a pulse frequency exactly by 10.
Hundreds
BCD counter D C B A D

Tens
BCD counter C B A D

Units
BCD counter C B A
Input

Decoder/display 0-9

Decoder/display 0-9

Decoder/display 0-9

Cascading BCD counters to count and display from 000 to 999.

MOD-60 COUNTER
MOD 6
___ CP1 ___ CPo
Q1 Qo not used MR 1

MOD 10
___ CP1 ___ CPo
Q1 Qo

7493

7493

MR 2 Q3

Q2

MR 2 Q3

Q2

fin

fout = fin/60

fin/10

Two 7493s can be combined to produce a MOD-60 Counter

DIGITAL CLOCK

COUNTERS
ASYNCHRONOUS
J Q CP K QN R S J Q CP K QN R S J Q CP K QN R S J Q CP K QN R S

SYNCHRONOUS
D S Q D S Q D S Q D S Q

CP QN R

CP QN R

CP QN R

CP QN R

SYNCHRONOUS COUNTERS
Two or more FFs connected as T FFs. All FFs in the counter are clocked at the same time. Advantage over the ripple counter is speed and accuracy but more complex.

5V S S S S

5V +V Q J CP QN K R Q J CP QN K R Q J CP QN K R Q J CP QN K R 0V

5V

SYNCHRONOUS COUNTERS N MOD <2

A NAND control gate is used to clear the counter before the full count.
5V +V

J CP QN K R

J CP QN K R

J CP QN K R

J CP QN K R 0V

SYNCHRONOUS COUNTERS UP/DOWN

0V 5V Q J CP QN K R 5V Q J CP QN K R Q J CP QN K R 0V

5V

PRESETTABLE COUNTERS
Can be preset to any desired count. To operate: 1. Apply desired count to parallel data inputs P2, P1, P0.

2. Apply a low pulse to the parallel load input PL.

P2 P1 Po PA RALLEL DA TA INPUTS

5V +V Q J CP QN K R S Q J CP QN K R S Q J CP QN K R 5V S

CLOCK PA RALLEL LOA D __ PL

COUNTER TYPES
Asynchronous Counter (a.k.a. Ripple or Serial Counter): each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain. Synchronous Counter (a.k.a. Parallel Counter): all the FFs in the counter are clocked at the same time. Up Counter: counter counts from zero to a maximum count. Down Counter: counter counts from a maximum count down to zero. BCD Counter: counter counts from 0000 to 1001 before it recycles. Pre-settable Counter: counter that can be preset to any starting count either synchronously or asynchronously Ring Counter: shift register in which the output of the last FF is connected back to the input of the first FF. Johnson Counter: shift register in which the inverted output of the last FF is connected to the input of the first FF.

74193 COUNTER
MOD-16 PRESETTABLE UP/DOWN COUNTER

RING COUNTER
Shift register counter with feedback from Q of last FF back to first FF input

RING COUNTER

5V

D 5V 0V

CP QN R

CP QN R

CP QN R

CP QN R

clk

JOHNSON COUNTER
Shift register in which the inverted output of the last FF is fed back to the input of the first FF.

5V

D 0V 0V

CP QN R

CP QN R

CP QN R

CP QN R

clk

Lab 18.

A PROGRAMMABLE COUNTER
Design a four-bit counter controlled by two control lines X and Y that behaves according to the truth table.

PROGRAM SWITCH X Y 0 0 0 1 1 0 1 1

COUNTER MODE NO COUNT MOD 5 MOD 10 MOD 12

Lab 18.

A PROGRAMMABLE COUNTER
5V Q1 CP1 Q2 CP2 S S S S Q

J CP QN K R

J CP QN K R

J CP QN K R

J CP QN K R

_ XY AC _ XY BD

XY CD

X Y

TNUOC ON 5 DOM 01 DOM 21 DOM RETNUOC EDOM

Y 0 1 0 1

MARGORP HCTI WS

X 0 0 1 1

RIPPLE COUNTER
Binary Output Clock Input

1111 0000

Pulse 1 8 7 6 5 4 3 2

PS and next clock pulse states and This theCLR input has 16(8) all FFs On 4-bit counter All J-K flip-flops in the will count are because each will receive will toggle binary 0000 through 1111 from INACTIVE a H-to-L pulse- one TOGGLE MODE and then reset back to another. after 0000. Watch the counthas a modulus of 16. The counter ripple thru the counter.

RIPPLE COUNTER WITH WAVEFORMS

Binary Output Clock Input

0011 100

Pulse 1 5 4 3 2

Clock input FFs triggered on 1s output H-to-L pulse. CLK toggles 1s FF. 1s FF toggles 2s FF.2s output 2s FF toggles 4s FF. 4s output

DECADE COUNTER
Binary Output Clock Input

1000 0111
Short negative pulse

Pulse 1 8 7 6 5 4 3 2

To clear input of each FF

All J & K inputs = 1 All PR inputs = 1

To change mod-16 counter to decade counter: Count is at 1001. Reset count to 0000 after 1001 (9) count. Next clock pulse will increment counter for a When count hits 1010 reset to 0000. short time to 1010 which will activate the NAND gate See added 2-input NAND gate that clears all and reset the counter to 0000. JK FFs to 0 when count hits 1010.

DOWN COUNTER
000 111

4 2 Pulse 1 5 3

Changes from Ripple Up Counter are wiring from Q outputs (instead of Q outputs) to the CLK input of the next FF.

SELF-STOPPING DOWN COUNTER

000 111

The count remained at binary 000.

4 3 2 Pulse 1 8 6 5 7

This is a 3-bit down counter. The 1s FF is in TOGGLE mode when counting (J & K = 1). The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate when the count decrements to 000. The count stops at 000.

COUNTER USED FOR FREQUENCY DIVISION

8 200 Hz 4

100 Hz
50 Hz 16
Clock Input

400 Hz
2

800 Hz

USING THE 7493 COUNTER IC

Counters are available in IC form. Either ripple (7493 IC) or synchronous (74192 IC) counters are available. 100 Hz ? Hz 400 Hz ? Hz 800 Hz ? Hz

1600 Hz

7493 Counter IC wired as a 4-bit binary counter

MAGNITUDE COMPARATOR
A magnitude comparator is a combinational logic device that compares the value of two binary numbers and responds with one of three outputs (A=B or A>B or A<B).

A(0) A(1)
Input binary 0111 Input binary 1111 Input binary 0001

A(2) A(3)

74HC85 Magnitude Comparator

A>B HIGH HIGH HIGH

B(0) B(1)
Input binary 0110 Input binary 1100 0111

A=B A<B

B(2) B(3)

TROUBLESHOOTING EQUIPMENT Logic Probe Logic Pulser Logic Clip (logic monitor) Digital IC Tester DMM/Logic Probe DMM or VOM Dual-trace Oscilloscope Logic Analyzer

SIMPLE TROUBLESHOOTING HINTS

Feel top of IC to determine if it is hot

Look for broken connections, signs of excessive heat Smell for overheating
Check power source

Trace path of logic through circuit

Know the normal operation of the circuit