Very Large Scale Integrated (VLSI) Circuits Technology

Prof. Dr. Taha Elsayed Taha

2011-2012

References
1- N. Weste and D Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition , Addison Wesley, 2011.
http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html

2- W. Wolf, Modern VLSI Design: Systems on Silicon, 3rd Edition, Prentice-Hall, 2002.

3- Muller R. and Kamins T., Device Electronics for Integrated Circuits, 3rd Edition, Wiley,2002.

Reference [1]:
http://www3.hmc.edu/~harris/cmos vlsi/4e/index.html N. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and System Perspective. Addison Wesley, 4th Edition, 2011. (ISBN 0-321-54774-8).

References

Copyright 2011 Pearson Education, Inc. Publishing as Pearson Addison - Wesley

Integrated Circuits (ICS) Overview

Moores Law

The number of transistors in an integrated circuit doubles every 2 years.

Moores Law. The number of transistors in an integrated circuit doubles every 2 years. years

Gigantic scale integration (GSI) :

2.

3.

Some Applications of VLSI Technology

Comparison between CMOS and Bipolar technologies

BJT Technology -The majority of bipolar transistors used in ICs are of the npn type because the higher mobility of minority carriers (electrons) in the base region results in higher speed performance than can be obtained with pnp types. - Lateral isolation is provided by oxide walls and vertical isolation is provided by the n p junction. -The lateral oxide isolation reduces the device size and the parasitic capacitance because of the smaller dielectric constant of silicon dioxide compared with silicon. - The first step is to form a buried layer. The main purpose of this layer is to minimize the series resistance of the collector.

MOS Technology There are three major MOS technology families: PMOS, NMOS and CMOS. They refer to the channel type of the MOS transistors made with the technology. - PMOS technology implement P-channel transistors by diffusing P-type dopants (usually Boron) into an N-type silicon substrate to form the source and the drain. P-channel is so named because the channel is composed of positively charged carriers. - NMOS technology are similar, but use N-type dopants (usually Phosphorus or Arsenic) to make N-channels transistors in P-type silicon substrate. Nchannel is so named because the channel is composed of negatively charged carriers. - CMOS (Complementary MOS) technology combine both P-channel and N-channel devices on the same silicon. Either P or N-type silicon substrates can be used. However, deep areas of the opposite doping type (called wells) must be defined to allow
fabrication of the complementary transistor type.Gate is made of polysilicon which is made up of multiple crystal structures, not a single crystal like the substrate. The poly is very heavily doped to be n+ so that it is a good conductor.

BiCMOS Technology
What is BiCMOS technology? BiCMOS technology combines Bipolar and CMOS transistors onto a single integrated circuit where the advantages of both can be utilized.

BiCMOS device structure

BiCMOS Advantages: Improved speed over CMOS Lower power dissipation than Bipolar Higher performance analog ICs Latch up immunity Flexible input/outputs

BiCMOS Disadvantages: Higher costs Longer fabrication cycle time

CMOS Fabrication Sequence The MOS process forms the foundation for CMOS technology. Figure a shows a CMOS inverter. The gate of the upper PMOS device is connected to the gate of the lower NMOS device. For the CMOS inverter, in either logic state, one device in the series path from VDD to ground is nonconductive. The current that flows in either steady state is a small leakage current, and only when both devices are on during switching does a significant current flow through the inverter. Thus, the average power dissipation is on the order of nanowatts. Low power consumption
is the most attractive feature of the CMOS circuit.

CMOS inverter: (a) circuit diagram; (b) layout; and (c) cross section