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What can eIectronic Photonic

Integration do for Energy


efficiency?
Luke Theogarajan
Itheogar@ece.ucsb.edu
With significant contributions form
Luis Chen (Ichen@ece.ucsb.edu)
utIine
Motivation
System Description
Circuits
Wafer-Scale ntegration
Future Work
The Growth of Data Consumption
Data traffic continues to grow
Data centers become key growth drivers
Kilper et, al., "Power Trends in Communication Networks, J.
Selected Topics in Quantum Electronics, March/April 2011
C. Lange et al., "Energy Consumption of Telecommunication
Networks and Related mprovement Options, J. Selected
Topics in Quantum Electronics, March/April 2011
Data Center Carbon Footprint
http://www.mckinsey.com/clientservice/bto/pointofview/pdf/BT_Data_Center.pdf
Power Consumption Breakdown
Source: Energy Logic: Reducing Data Center Energy Consumption by
Creating Savings that Cascade Across Systems, Emerson Power
The Cascade Effect
Source: Energy Logic: Reducing Data Center Energy Consumption by
Creating Savings that Cascade Across Systems, Emerson Power
Data Center Switches
Demand is
outpacing capacity
by more than 10x
Energy Savings pportunities
http://www1.eere.energy.gov/industry/datacenters/pdfs/vision_and_roadmap.pdf
Big Opportunities!
EIectronic Switch for Data Centers
Full P routing
Enhanced security
Scalable by parallelism
Cisco CRS-3, 4.48Tbps, Power ~ 10kW
Scalable up to 322Tbps, but would consume 700kW!
CSCO. (2010). CSCO CRS-3 carrier routing system.
http://www.cisco.com/en/US/products/ps5763/products_data_sheets_list.html
Difficult to scale to satisfy demand due to power constraints
CMS ScaIing
Kilper et, al., J. Selected Topics in Quantum Electronics,
March/April 2011
S.J. Ben Yoo, J. Selected Topics in Quantum Electronics,
March/April 2011
EIectricaI vs pticaI Interconnect
Exceeds TRS Roadmap!
Limit of the TRS Roadmap
Proposed SoIution
Electronic switch difficult to scale to meet demand and satisfy
power constraints
Optical switching can solve bandwidth requirement
Current generation MEMS based switch is slow
Semiconductor Optical Amplifier based switch fabric is fast but power
hungry
We propose deep integration of CMOS electronic with Hybrid
silicon photonic switch to achieve both capacity and low power
solution
#esearch GoaIs
Develop Highly ntegrated CMOS Circuits To Enable Energy
Efficient Fast Optical Packet Switching
Area efficient, Low-power Switch Driver
Novel Fully Differential Transimpedance Amplifier Circuit
Multi-Channel ntegrated Optical Frontend (TA/Limiting Amp/CDR)
System Demonstration of 4x4, 8x8 Optical Packet Switch (in
collaboration with Aurrion nc.)
Output Power Equalization
Routing using CMOS+FPGA
Demonstrate Feasibility and Energy Efficiency of Wafer-scale
ntegration of CMOS and Photonic C (With Collaboration)
n Integrated pproach
System rchitecture
Circuit ImpIementation
Low Power Optical Switch Driver
Novel Fully Differential TA circuit
ntegrated Optical Frontend
Clock and Data Recovery
Luis Chen
The pticaI Switch
"High-Speed Hybrid SiIicon Mach-Zehnder ModuIator and
TunabIe Microwave FiIter"
Hui-Wen Chen, Ph. D. Thesis UC, Santa Barbara
Low Power Switch Driver
Adjustable output voltage (1 to 3.3V)
Fast rise time (<5ns)
nterference mmunity (PSRR)
Low power consumption (150W DC)
Turbo Controller
Switch Load
Regulated nverter
Output
Vin
Vout
Schematic
Output adjustable using Vref
Turbo mode provides ~10ns initial power boost
AZC adjusts zero location to guarantee stability
Layout
91 m
113 m
SimuIated #esuIt
Current Boost
Low Current
FuIIy DifferentiaI TI
True differential outputs
Superior ground/supply noise rejection
Fully differential implementation is more resilient to wire cross-coupling and
noise injection
Reduces Channel-to-Channel interference, hence suitable to multi-channel
chip implementation
TI Circuit Schematic
TA Core
Transimpedance mpIifier
AC Small Signal Simulation
TA Gain vs Frequency
W/Layout parasitics
BW ~ 1.7 GHz, 500 fF Cin
150 m
73 m
TI Transient SimuIation
10 Gbps PRBS Output Eye Diagram
nput = 10A
True-Differential Output Data Stream 4.4mV Differential Output
Power SuppIy #ejection
RGC-based Differential TA can reject supply/gnd noise, but
BW is limited to RC filter cutoff freq, typically few MHz.
Proposed TA PSRR BW > 1GHz vs ~MHz of RGC TA
RGC Diff TA
Proposed TA
Input #eferred Noise Current
50pA/\Hz to 168pA/\Hz from 10MHz to 10GHz
(Differential)
Limiting mpIifier Design
4 Stage Active Feedback Cherry-Hooper
Negative Miller Capacitance to reduce loading
TILimiting mpIifier
4-stage Limiting Amplifier
50 D Driver outputs 245mVpp for measurement
330 m
100 m
naIog Frontend Transient Sim
10 Gbps PRBS
Output Eye Diagram
#x Frontend SimuIation
Measurements
Switch Driver
Electrical
Optical
Differential TA (S-Parameters)
TA+LA (S-Parameters)
TA
TA+LA S
w
i
t
c
h

D
r
i
v
e
r
s
n-Wafer S-params Measurements
Transimpedance
Measurement Setup
Supply Rejection
Measurement Setup
3-Port mixed mode S-parameters
)
33 32 23 22
(
2
1
)
31 21
(
2
1
1
S S S S
dd
S
S S
d
S
+ =
=
Diff. nsertion Gain
Diff. Output Return Loss

7
d
d
Delay Group
d
S
S
S
Z
d
S Z Ztd
=

+
= =

'
+

'


1
11 1
11 1
0 1 11
Transimpedance and Group Delay
TI S-parameters
Measured 3-Port mixed mode s-parameters
Very good agreement with simulated results
Measured S-parameters
Transimpedance/Group DeIay
Differential Zt ~ 57dBD, BW ~ 1.65 GHz with 500fF C
in
Group delay ~ 200 pS
Simulated
Measured
Simulated
Measured
SuppIy #ejection
Sd1 parameters with input port on supply
SimuIated Input #eferred Noise
Simulated n-band noise ~ 18 pA/\Hz
100MHz to 2 GHz, total
npp
=5.2A
TIL Measurement
Result is less ideal
Suspect supply injection
Measured S-parameters
S
d1
S
11
S
dd
Ztd ~ 67dBD
Group Delay
Switch Driver Measurements
fin = 20 MHz, vref=1.5V, 2V, 2.5V and 3V
Active probe attenuation = 11.764X
C
load
~ 2pF (0.7pF from probe)
0
1
2
3
4
3
6
7
0 1 2 3 4
k
|
s
e

1
|
m
e

(
n
s
)
keference Vo|tage (V)
Measured SlmulaLed
pticaI Switch w/CMS Driver
nput at Port 1, Out at Port 3
Reverse Bias 3.5V
Trise ~ 6ns
1mV/div
20ns/div
-300
-200
-100
0
100
200
300
400
500
600
18.06 18.07 18.08 18.09

m
p
I
i
t
u
d
e

(

V
)
Time (S)
Optical
response
Hybrid Silicon
Optical Switch
CMOS Driver
P
1
P
3
Power Comparisons
ChanneIs 2 4 8 36
TI/L/CD# 10 20 40 180
Laser Driver 100 200 400 1800
FPG 100 200 400 1800
Switch Driver 1 1 1 1
200 400 800 3600
CaIibration 5 10 20 90
TotaI (W) 0.416 0.831 1.661 7.471
*CommerciaI EIectronic
Switch 36x36 (W) 85
Optical amplifiers and FPGA dominate the power consumption
10X Reduction at comparable throughput compared to commercial part
Power is independent of data rate can scale to much higher data rate
EIectronic Photonic Integration
4 Current Approaches
4 Heterogeneous ntegration
4 Future Work
Front-End of the Line Integration
Prototype 10-Gb/s transceiver from Luxtera Corporation
Luxtera's EIectronic Photonic
Integration
Source: http://members.infinibandta.org/kwspub/Luxtera.pdf
TechnoIogy
All devices are co-fabricated on a standard CMOS line
ey Components
Limitations
Development cost is very high
Does not leverage the latest advances in CMOS
Optical Waveguides below metallization
HeIios: pHotonics ELectronics
functionaI Integration on CMS
Silicon Photonic Circuits: On-CMOS ntegration, Fiber Optical Coupling, and
Packaging, Kopp et. al, EEE JOURNAL OF SELECTED TOPCS N QUANTUM
ELECTRONCS, VOL. 17, NO. 3, MAY/JUNE 2011
bove IC Photonic integration
nP dies bonded
after last level
metallization
CMS IC Preparation
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Bond and Etch Photonic waveguides
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
ModuIator
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Photodetector
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Mirror
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Bonding
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Substrate #emovaI
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
InP Device Bonding
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Heterostructure Processing
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Via Definition
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
MetaI deposition
Source: Jean-Marc FEDEL, "Si and nP
ntegration in the HELOS project, (invited),
presented at ECOC 2009, 20-24 September
2009, Vienna (Austria)
Limitations
Total of 5 sophisticated processing steps after CMOS
and Photonic wafer are bonded together, could
potentially lead to yield issues
Need close integration with commercial CMOS
foundry, may not be cost-effective.
Wafer-ScaIe pproach
Photonics and Electronics function at different length
scales so a better approach would be post fabrication
integration
Can we take a parallel rather serial approach?
Can we integrate foundry CMOS die with foundry
photonics?
Advantages:
Leverage best CMOS and photonic technology
Disadvantage
Larger package size
Possible issues with waveguides
Ashfaque Udiin
Photonic CMOS Chip Integration
8de vew
Slot in and Wire
CMOS Foundry Chips
Hybrid -V Photonics Silicon Wafer
Chip
Negative Resist
Photonic WaIer (a) Expose resist
(b) Develop resist
(c) ICP etch oxide
Make chip speciIic pit in the holder waIer such that the gap between
the chip and the holder waIer is as small as possible (5-10 m)
Oxide
Chip Integration: Making A Chip Specific Pit (1)
Frcccss Elcw
(d) Strip oII resist
(e) Bosch etch silicon
(I) BuIIered HF etch oxide
Photonic WaIer
Oxide
Chip Integration: Making A Chip Specific Pit (2)
Microscope Image: Chip placed in holder wafer (Top view)
Holder Wafer
Chip
Gap
Chip Integration: Making A Chip Specific Pit
Frcccss Rcsults
um
2 um
3 um
2 um
Microscope Image: Chip corners
Chip Integration: A Making Chip Specific Pit
Chip Integration: Bonding & Planarization
Carrier waIer
BCB
Support waIer
c h i p P h o t o n i c w a I e r
(a) Place chip and holder waIer Iaced upside down on a support waIer
(b) Spin BCB on a carrier waIer
Frcccss Elcw
c a r r i e r w a I e r
B C B
Support waIer
c h i p P h o t o n i c w a I e r
(c) Flip the BCB coated carrier waIer, and bond it on the backside oI
the holder waIer and the chip using a Ilipchip bonder
Chip Integration: Bonding & Planarization
Carrier waIer
BCB
chip Photonic waIer
(d) Remove the bonded sample Irom the support waIer, and Ilip
Chip Integration: Bonding & Planarization
Carrier waIer
BCB
chip Photonic waIer
SOG
(e) Spin SOG twice to Iill the gap, and planarize
Carrier waIer
BCB
chip Photonic waIer
Carrier waIer
BCB
chip Photonic waIer
(I) Etch back SOG
(g) Spin SOG to planarize
5.3 m
22 m
10 m
Chip Integration: Bonding & Planarization
Chip
Dummy
SiIicon
Wafer
Carrier
SG
BCB
Frcccss Rcsults
SEM image: Cross-section
1.5 m
SG
Chip Integration: Bonding & Planarization (5)
Chip
HoIder
SEM image: Top-view
InterIace
SG
Dektak proIile
1 m
.5 m
Holder
Chip
Interface
Carrier waIer
BCB
chip Holder waIer
(a) Etch SOG to open aluminum pads
Carrier waIer
BCB
chip Holder waIer
(b) Sputter deposit Ti/Au
Carrier waIer
BCB
chip Holder waIer
(c) Etch and pattern Au/Ti
Contacts On ntegrated Chip
Frcccss Elcw
MetaIIized Foundry Chip in SiIicon
Wafer
A. Uddin, K. Milaninia, C.-H. Chen, and L. Theogarajan. Components, Packaging and
Manufacturing Technology, IEEE Transactions on, PP(99):1, 2011.
Future Work
Design and ntegration of CMOS processing circuits
with Photonic switches
Separate waveguide layer integration
ConcIusions
There is plenty of power savings to be had that can
have tremendous impact on data centers
Photonic interconnect is the most promising approach
to achieving these goals
Close heterogeneous integration of CMOS will enable
the next generation of integrated photonic switches.
cknowIedgements
Prof. John Bowers
Aurrion- Greg Fish, Alex Fang and Eric Hall
Graduate Students - Luis Chen, Ashfaque Uddin
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