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8051 interrupts
8051 has six interrupts. The occurrence of any interrupt will cause the control of program to shift to the corresponding ROM location given in the vector table
Vector Table
Interrupts
Reset
Pin
9 P3.2 (12)
Flag Clearing
Auto Auto
External Hardware 0003 Interrupt 0 (INT 0 or EX0) Timer 0 interrupt (TF0) 000B
External Hardware 0013 Interrupt 1 (INT 1 or EX1) Timer 1 interrupt (TF1) Serial Comm interrupt (RI & TI) 001B 0023
8051Interrupts
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Vcc 40 P0.0(AD0) 39 P0.1(AD1) 38 P0.2(AD2) 37 P0.3(AD3) 36 P0.4(AD4) 35 P0.5(AD5) 34 P0.6(AD6) 33 P0.7(AD7) 32 31 EA/VPP ALE/PROG 30 Internal 29 PSEN Interrupts P2.7(A15) 28 P2.6(A14) 27 P2.5(A13) 26 P2.4(A12) 25 P2.3(A11) 24 P2.2(A10) 23 P2.1(A9) 22 P2.0(A8) 21
8051 (8031)
TF0
External interrupts
TF1 RI & TI
-----
ET2
Timer#2 8052 C
ES
Serial comm
ET1
Timer 1
EX1
External Interrupt 1
ET0
Timer 0
EX0
External Interrupt 0
GATE =1
C/T
M1
M0
GATE =1
C/T
M1
M0
Edge triggered
TF1
TR1 TF0
TR0 IE1
IT1
or
IE0
IT0
IT0 = INTR0(pin 3.2) type control bit. 1 for low edge triggered & 0 for low level triggered. IT1 = INTR1(pin 3.3) type control bit. 1 for low edge triggered & 0 for low level triggered.
-----------------4 MC
IT0
----------RETI
Priorities of Interrupts
8051 has six interrupts with the default priorities as given the table below. If any interrupt occurs it will be serviced according to its priority. If the processor is servicing any high priority interrupt & mean while low priority interrupt occurs it will be pended till high priority Interrupt is serviced. However during the service of low priority interrupt, the occurrence of high priority interrupt will cause the control to shift to high prioritys ISR.
Priorities of Interrupts
Priority
Highest
Interrupt
Reset External Hardware Interrupt 0 (INT 0 or EX0) Timer 0 interrupt (TF0) External Hardware Interrupt 1 (INT 1 or EX1) Timer 1 interrupt (TF1)
PS
PT1
PX1
PT0
PX0
Look the sequence of second & third interrupts, although they are on the top of the list but their order is according to the default sequence. No Interrupt can supercede the RESET priority.