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8051 Interrupts

8051 interrupts
8051 has six interrupts. The occurrence of any interrupt will cause the control of program to shift to the corresponding ROM location given in the vector table

Vector Table
Interrupts
Reset

ROM location (H)


0000

Pin
9 P3.2 (12)

Flag Clearing
Auto Auto

External Hardware 0003 Interrupt 0 (INT 0 or EX0) Timer 0 interrupt (TF0) 000B

Auto P3.3 (13) Auto

External Hardware 0013 Interrupt 1 (INT 1 or EX1) Timer 1 interrupt (TF1) Serial Comm interrupt (RI & TI) 001B 0023

Auto Programmer clears it

8051Interrupts
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Vcc 40 P0.0(AD0) 39 P0.1(AD1) 38 P0.2(AD2) 37 P0.3(AD3) 36 P0.4(AD4) 35 P0.5(AD5) 34 P0.6(AD6) 33 P0.7(AD7) 32 31 EA/VPP ALE/PROG 30 Internal 29 PSEN Interrupts P2.7(A15) 28 P2.6(A14) 27 P2.5(A13) 26 P2.4(A12) 25 P2.3(A11) 24 P2.2(A10) 23 P2.1(A9) 22 P2.0(A8) 21

8051 (8031)
TF0

External interrupts

TF1 RI & TI

The main condition


No Interrupting signal can interrupt processor till its corresponding bit as well as EA (Enable All) bit in IE register is high. EA
Global enable

-----

ET2
Timer#2 8052 C

ES
Serial comm

ET1
Timer 1

EX1
External Interrupt 1

ET0
Timer 0

EX0
External Interrupt 0

Interrupt Enable register (bit addressable)

Timer Overflow Interrupts


The processor is busy in checking TF0 flag, Wastage of its time in JNB TF0, $ Solution? Set ET1 for timer 1 & ET 0 for timer 0, so when EA is high (compulsory for all interrupts to be effective) the processor will be interrupted when Timer overflows & jumps to ISR addresses already specified e.g MOV IE, # 10001000B ; timer 1 overflow will cause interruption

Interrupt vectors when timer overflows


Timer 0 interrupt vector TF 0
1 000B H

Timer 1 interrupt vector TF 1


1 001B H

TF is automatically cleared when the control transfers to ISR.

External hardware interrupts INT0 & INT1


There are 2 external hardware interrupts. 1. INT0 also called EX0 on pin 3.2 2. INT1 also called EX1 on pin 3.3

Externally stopping & restarting Timers/Counters


These interrupts apart from several other uses can be used to stop the counting of timers/counters by giving a low pulse or falling edge (whatever is the type selected) to the external pin

Timer without external control


Timer will keep running till it overflows

Gate Bit for timer external control


The G bit of TMOD register must be high if the timer has to be controlled externally.

GATE =1

C/T

M1

M0

GATE =1

C/T

M1

M0

Exxternal hardware interrupts to stop & restart counter


P3.2 (INTR 0 or EX0) 02H 01 00H 04H 03H 8051

Edge triggered

Selecting Type of External interrupt INTx


Whether INTRx should be level or edge triggered)?
TCON (timer control) (bit addressable)

TF1

TR1 TF0

TR0 IE1

IT1
or

IE0

IT0

IT0 = INTR0(pin 3.2) type control bit. 1 for low edge triggered & 0 for low level triggered. IT1 = INTR1(pin 3.3) type control bit. 1 for low edge triggered & 0 for low level triggered.

Level Triggered interrupt


The interrupting signal must be low for 4 MC before start of execution of ISR & no more. If it remains low till the end of ISR, it will be considered as a new interrupt.
0003 ISR for INT0 P3.2 (INT0) 8051 0300 Main prog ----------

-----------------4 MC

Edge triggered Interrupt


Put 1 in IT0 or IT1 for selecting falling edge type of triggering for pins INT0 & INT 1 respectively. The low signal is latched in IE0 & IE 1 of TCON register till the end of ISR. No new falling signal at these pins will trigger new interrupt till IE0 & IE1 will be cleared. The interrupting signal must be high for at least 1 MC & then low for at least 1 MC. IE0 & IE 1 are called interrupt in service bits as they show that interrupt service is in process & no new interrupt signal will be serviced. However when ISR is finished IE0 & IE1 will be cleared automatically.

IN Service Bits IEx


TF1 TR1 TF0 TR0 IE1 IT1 IE0
=1

IT0

0003 ISR of INT 0 -----------------------

----------RETI

Priorities of Interrupts
8051 has six interrupts with the default priorities as given the table below. If any interrupt occurs it will be serviced according to its priority. If the processor is servicing any high priority interrupt & mean while low priority interrupt occurs it will be pended till high priority Interrupt is serviced. However during the service of low priority interrupt, the occurrence of high priority interrupt will cause the control to shift to high prioritys ISR.

Priorities of Interrupts
Priority
Highest

Interrupt
Reset External Hardware Interrupt 0 (INT 0 or EX0) Timer 0 interrupt (TF0) External Hardware Interrupt 1 (INT 1 or EX1) Timer 1 interrupt (TF1)

Lowest Timer 2 (8052 only)

Serial Comm interrupt (RI & TI) Timer 2 interrupt (TF2)

Changing the default priorities


--------PT2
Timer#2 8052 C

PS

PT1

PX1

PT0

PX0

PT2 = Timer 2 Interrupt priority

PS = Serial port Interrupt priority


PT1 = Timer 1 Interrupt priority PX 1=External Interrupt 1 Interrupt priority PT 0 =Timer 0 Interrupt priority PX 0= 1=External Interrupt 0 Interrupt priority Setting any bit to 1 will shift it to Top most position in the Interrupt table below RESET, while the sequence of other interrupts will be un disturbed.

Changing priorities of 2 interrupts


Example MOV IP, #00001100B The new priority table starting from highest priority will be
1. 2. 3. 4. 5. 6. 7. Reset External Hardware Interrupt 1 (INT 1 or EX1) Timer 1 interrupt (TF1) External Hardware Interrupt 0 (INT 0 or EX0) Timer 0 interrupt (TF0) Serial Comm interrupt (RI & TI) Timer 2 interrupt (TF2)

Look the sequence of second & third interrupts, although they are on the top of the list but their order is according to the default sequence. No Interrupt can supercede the RESET priority.

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