Hi-Impedance Outputs

Logic gates introduced thus far

have 1 and 0 output values, cannot have their outputs connected together, and transmit signals on connections in only one direction.

Three-state logic adds a third logic value, HiImpedance (Hi-Z), giving three states: 0, 1, and Hi-Z on the outputs. The presence of a Hi-Z state makes a gate output as described above behave quite differently:
1 and 0 become 1, 0, and Hi-Z cannot becomes can, and only one becomes two
Chapter 2 - Part 3 1

Hi-Impedance Outputs (continued)

What is a Hi-Z value?

The Hi-Z value behaves as an open circuit This means that, looking back into the circuit, the output appears to be disconnected. It is as if a switch between the internal circuitry and the output has been opened.

Hi-Z may appear on the output of any gate, but we restrict gates to:
a 3-state buffer, or Optional: a transmission gate (See Reading Supplement: More on CMOS Circuit-Level Design),

each of which has one data input and one control input.

Chapter 2 - Part 3

The 3-State Buffer

For the symbol and truth table, IN Symbol is the data input, and EN, the control input. IN OUT For EN = 0, regardless of the value on IN (denoted by X), the output EN value is Hi-Z. Truth Table For EN = 1, the output value follows the input value. EN IN OUT Variations: 0 X Hi-Z Data input, IN, can be inverted Control input, EN, can be inverted 1 0 0 by addition of bubbles to signals. 1 1 1

Chapter 2 - Part 3

Resolving 3-State Values on a Connection

Connection of two 3-state buffer outputs, B1 and B0, to a wire, OUT Assumption: Buffer data inputs can take on any combination of values 0 and 1 Resulting Rule: At least one buffer output value must be Hi-Z. Why? How many valid buffer output combinations exist? What is the rule for n 3-state buffers connected to wire, OUT? How many valid buffer output combinations exist?
Chapter 2 - Part 3 4

Resolution Table B1 0 1 Hi-Z Hi-Z B0 Hi-Z Hi-Z 0 1 OUT 0 1 0 1

Hi-Z Hi-Z Hi-Z

3-State Logic Circuit

Data Selection Function: If s = 0, OL = IN0, else OL = IN1 Performing data selection with 3-state buffers: EN0 0 0 1 IN0 X X 0 EN1 1 1 0 IN1 0 1 X OL 0 1 0
S IN0 EN0
OL

1 1 0 X 1 IN1 EN1 0 X 0 X X Since EN0 = S and EN1 = S, one of the two buffer outputs is always Hi-Z plus the last row of the table never occurs.

Chapter 2 - Part 3

Decoding
Decoding - the conversion of an n-bit input code to an m-bit output code with n em e 2n such that each valid code word produces a unique output code Circuits that perform decoding are called decoders Here, functional blocks for decoding are
called n-to-m line decoders, where m e 2n, and generate 2n (or fewer) minterms for the n input variables
Chapter 3 6

Decoder Examples
1-to-2-Line Decoder
A 0 1 D0 D1 D0 = A 1 0 (a) 0 1 A (b) D1 = A

2-to-4-Line Decoder
A0 A1 A0 0 0 1 1 0 1 0 1 D0 D 1 D2 D3 A1 1 0 0 0 (a) 0 1 0 0 0 0 1 0 0 0 0 1

D0 = A 1 A 0 D1 = A 1 A 0 D2 = A 1 A 0 D3 = A 1 A 0 (b)

 Note that the 2-4-line

made up of 2 1-to-2line decoders and 4 AND gates.
Chapter 3 7

Decoder Expansion
General procedure given in book for any decoder with n inputs and 2n outputs. This procedure builds a decoder backward from the outputs. The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1. These decoders are then designed using the same procedure until 2-to-1-line decoders are reached. The procedure can be modified to apply to decoders with the number of outputs 2n

Chapter 3 8

Decoder Expansion - Example 1

3-to-8-line decoder
Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal
2-to-4-line decoder 1-to-2-line decoder

2-to-4-line decoder
Number of output ANDs = 4 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal
Two 1-to-2-line decoders

See next slide for result

Chapter 3 9

Decoder Expansion - Example 1

4 2-input A Ds 8 2-input A Ds

Result

A0

D0
D1

A1

D2 2-to-4-Line decoder
D3 D4

A2

D5 1-to-2-Line decoders D6 D7

Chapter 3 10

3-to-8 Line decoder

Decoder Expansion - Example 2

7-to-128-line decoder
Number of output ANDs = 128 Number of inputs to decoders driving output ANDs = 7 Closest possible split to equal
4-to-16-line decoder 3-to-8-line decoder

4-to-16-line decoder
Number of output ANDs = 16 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal
2 2-to-4-line decoders

Complete using known 3-8 and 2-to-4 line decoders

Chapter 3 11

Decoder with Enable

In general, attach m-enabling circuits to the outputs See truth table below for function
Note use of X s to denote both 0 and 1 Combination containing two X s represent four binary combinations

Alternatively, can be viewed as distributing value of signal EN to EN 1 of 4 outputs A In this case, called a A demultiplexer D
1 0 0

EN A 1 A 0 0 1 1 1 1
Chapter 3 12

D0 D1 D2 D3 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1

D1

X 0 0 1 1

X 0 1 0 1

D2

D3 (b)

(a)

Encoding
Encoding - the opposite of decoding - the conversion of m discrete inputs to a n-bit output code with n em e 2n such that each of the inputs produces a unique output code Circuits that perform encoding are called encoders An encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corres-ponding to the position in which the 1 appears. Two types - inputs mutually exclusive or not

Chapter 3 13

Encoder Example
A decimal-to-excess 3 BCD encoder
Inputs: 10 bits corresponding to decimal digits 0 through 9, (D0, , D9) Outputs: 4 bits with excess 3 BCD codes Function: If input bit Di is a 1, then the output (A3, A2, A1, A0) is the excess 3 BCD code for i D i A3 A2 A1 A0 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0

Chapter 3 14

Encoder Example (continued)

Input Di is a term in equation Aj if bit Aj is 1 in the binary value for i. Equations:
A3 = D5 + D6 + D7 + D8 + D9 A2 = D1 + D2 + D3 + D4 + D9 A1 = D0 + D3 + D4 + D7 + D8 A0 = D0 + D2 + D4 + D6 + D8

Note that if none of the inputs are asserted the output = "0000" (invalid excess 3 code)
Chapter 3 15

Selecting
Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have:
A set of inputs from which the selection is made A single output A set of control lines for making the selection

Logic circuits that perform selecting are called multiplexers Selecting can also be done by three-state logic or transmission gates
Chapter 3 16

Multiplexers
A multiplexer selects information from an input line and directs the information to the output line A typical multiplexer has n control inputs (Sn  1, S0) called selection inputs, 2n information inputs (I2n  1, I0), and one output Y A multiplexer can be designed to have m information inputs with m 2n as well as n selection inputs

Chapter 3 17

2-to-1-Line Multiplexer
Since 2 = 21, n = 1 The single selection variable S has two values:
S = 0 selects input I0 S = 1 selects input I1

The equation: S Y = I0 + SI1 The circuit:

S

Decoder
I0

Enabling Circuit

I1
Chapter 3 18

2-to-1-Line Multiplexer (continued)

Note the regions of the multiplexer circuit shown:
1-to-2-line Decoder 2 Enabling circuits 2-input OR gate

To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 v 2 AND-OR circuit:
1-to-2-line decoder 2 v 2 AND-OR

In general, for an 2n-to-1-line multiplexer:

n-to-2n-line decoder 2n v 2 AND-OR
Chapter 3 19

Example: 4-to-1-line Multiplexer

2-to-22-line decoder 22 v 2 AND-OR
S1 S0
S1 S0 Decoder

Decoder 4 X2 AND-OR I0 I1 I2 I3
Y

Chapter 3 20

Multiplexer Width Expansion

Select vectors of bits instead of bits Use multiple copies of 2n v 2 AND-OR in parallel Example: 4-to-1-line quad multiplexer
AN OR I 0,0

. . .

Y0

I 3,0

43

AN

OR

A0

. . .

. . .

A1

Chapter 3 21

I 3,

I 0,

Y1

43 I 0,2 . . .

AN

OR Y2

I 3,2
I 0,3 . . . I 3,3

43

AN

OR

Y3

Other Selection Implementations

Three-state logic in place of AND-OR S
0

I0

I1
1

I2
I3

(b) Gate input cost = 14 compared to 22 (or 18) for gate implementation

Chapter 3 22

Functional Blocks: Addition

Binary addition used frequently Addition Development:
Half-Adder (HA), a 2-input bit-wise addition functional block, Full-Adder (FA), a 3-input bit-wise addition functional block, Ripple Carry Adder, an iterative array to perform binary addition, and Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance.
Chapter 4 23

Functional Block: Half-Adder

A 2-input, 1-bit width binary adder that performs the following computations: X 0 0 1
+Y CS +0 00 +1 01 +0 01 1 +1 10

A half adder adds two bits to produce a two-bit sum X Y C S The sum is expressed as a sum bit 0 0 0 0 , S and a carry bit, C 0 1 0 1 The half adder can be specified as a 1 0 0 1 truth table for S and C 1 1 1 0
Chapter 4 24

Logic Simplification: Half-Adder

The K-Map for S, C is: This is a pretty trivial map! By inspection:
C
0

Y
0 1

11
3

S ! X Y  X Y ! X Y S ! (X  Y ) (X  Y )
and

12

13

C ! X Y C ! ( ( X Y ) )

These equations lead to several implementations.

Chapter 4 25

Five Implementations: Half-Adder

We can derive following sets of equations for a half-adder:

(d) S ! ( X  Y ) C ( a) S ! X Y  X Y C ! (X  Y ) C ! X Y ( b ) S ! ( X  Y ) ( X  Y ) ( e) S ! X Y C ! X Y C ! X Y (c) S ! (C  X Y ) (a),C ! and Y are SOP, POS, and XOR implementations (b), X (e)
for S. In (c), the C function is used as a term in the AND-NOR implementation of S, and in (d), the function is used in a C POS term for S.
Chapter 4 26

Implementations: Half-Adder
The most common half implementation is:

X Y

adder (e)

S C

S ! X Y C ! X Y
A NAND only implementation is:

C S

S ! (X  Y ) C C ! ( ( X Y ) )

Chapter 4 27

Functional Block: Full-Adder

A full adder is similar to a half adder, but includes a carryin bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. Z 0 0 0 For a carry-in (Z) of 0, X 0 0 1 it is the same as the half-adder: +Y +0 +1 +0 CS For a carry- in (Z) of 1: Z X +Y CS
Chapter 4 28

0 1 +1 10 1 1 +1 11

00 1 0 +0 01

01 1 0 +1 10

01 1 1 +0 10

Logic Optimization: Full-Adder

Full-Adder Truth Table:
X Y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
C Y

Full-Adder K-Map:
S Y

Z 0 1 0 1 0 1 0 1

C 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

1
0 1 3

1
2 0 1 5

1
3 2 6

14

17

15 17 16
Z

Z
Chapter 4 29

Implementation: Full Adder

Full Adder Schematic Here X, Y, and Z, and C (from the previous pages) are A, B, Ci and Co, respectively. Also, G = generate and P = propagate. Note: This is really a combination of a 3-bit odd function (for S)) and Carry logic (for Co):
Co ! G + P Ci
Chapter 4 30

Ai Bi Gi

Pi

Ci

Ci+ 1 (G = Generate) OR (P =Propagate AND C = Carry In)

i

Si

Binary Adders
To add multiple operands, we bundle logical signals together into vectors and use functional blocks that operate on the vectors
Description Carry In Augend Addend Sum Carry out

Example: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector S(3:0) Note: carry out of cell i becomes carry in of cell i+1

Subscript 3210 0110 1011 0011 1110 0011

Name Ci Ai Bi Si Ci+1

Chapter 4 31

4-bit Ripple-Carry Binary Adder

A four-bit Ripple Carry Adder made from four 1bit Full Adders:
B3
3

B2

B1

C3

C2

C1

S3

S2

S1

Chapter 4 32

Complements
Two complements:
Diminished Radix Complement of N
(r  1) s complement for radix r 1 s complement for radix 2 Defined as (rn    2

Radix Complement
r s complement for radix r 2 s complement in binary Defined as rn  N

Subtraction is done by adding the complement of the subtrahend If the result is negative, takes its 2 s complement
Chapter 4 33

Binary 1's Complement

For r = 2, N = 011100112, n = 8 (8 digits): (rn 1) = 256 -1 = 25510 or 111111112 The 1's complement of 011100112 is then: 11111111 01110011 10001100 Since the 2n 1 factor consists of all 1's and since 1 0 = 1 and 1 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT).
Chapter 4 34

Binary 2's Complement

For r = 2, N = 011100112, n = 8 (8 digits), we have: (rn ) = 25610 or 1000000002 The 2's complement of 01110011 is then: 100000000 01110011 10001101 Note the result is the 1's complement plus 1, a fact that can be used in designing hardware
Chapter 4 35

Alternate 2 s Complement Method

Given: an n-bit binary number, beginning at the least significant bit and proceeding upward:
Copy all least significant 0 s Copy the first 1 Complement all bits thereafter.

2 s Complement Example:
10010100 Copy underlined bits: 100 and complement bits to the left: 01101100
Chapter 4 36

Subtraction with 2 s Complement

For n-digit, unsigned numbers M and N, find M  N in base 2:
Add the 2's complement of the subtrahend N to the minuend M: M + (2n  N) = M  N + 2n If M " N, the sum produces end carry rn which is discarded; from above, M  N remains. If M < N, the sum does not produce an end carry and, from above, is equal to 2n  ( N  M ), the 2's complement of ( N  M ). To obtain the result  (N M) , take the 2's complement of the sum and place a  to its left.
Chapter 4 37

Unsigned 2 s Complement Subtraction Example 1

Find 010101002 010000112

1

01010100 2 s comp + 10111101 00010001 The carry of 1 indicates that no correction of the result is required.

01010100 01000011

Chapter 4 38

Unsigned 2 s Complement Subtraction Example 2

Find 010000112 010101002

0

01000011 2 s comp 10101100 + 11101111 2 s comp 00010001 The carry of 0 indicates that a correction of the result is required. Result = (00010001)
Chapter 4 39

01000011 01010100

2 s Complement Adder/Subtractor
Subtraction can be done by addition of the 2's Complement. 1. Complement each bit (1's Complement.) 2. Add 1 to the result. The circuit shown computes A + B and A B: For S = 1, subtract, the 2 s complement B A B A B A of B is formed by using B A XORs to form the 1 s comp and adding the 1 applied to C0. For S = 0, add, B is passed through C C C unchanged A FA FA FA
3 3 2 2 1 1 0

C0

C4

S3

S2

S1

S0

Chapter 4 40

Introduction to Sequential Circuits

Inputs

A Sequential circuit contains:

Storage Storage elements: Elements Latches or Flip-Flops Combinational Logic:

Combinational Logic State Next State

Outputs

Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements.
Chapter 5 - Part 1 41

Introduction to Sequential Circuits

Inputs Storage Elements Combinational Logic State Next State Outputs

Combinatorial Logic Next state function

Next State = f(Inputs, State) Output function (Mealy) Outputs = g(Inputs, State) Output function (Moore) Outputs = h(State) Output function type depends on specification and affects the design significantly
Chapter 5 - Part 1 42

Basic (NAND) S R Latch

Cross-Coupling NAND gates gives Latch: Which has the time sequence behavior:
1 1 1 0 1 0 1
S (set)

twoQ the S -R
Q

R (reset)

Time R S Q Q Comment
1 0 1 1 1 0 1 ? 1 1 0 0 1 ? ? 0 0 1 1 1 ? Stored state unknown Set Q to 1 Now Q remembers 1 Reset Q to 0 Now Q remembers 0 Both go high Unstable!

S = 0, R = 0 is forbidden as input pattern

Chapter 5 - Part 1 43

Basic (NOR) S R Latch

Cross-coupling two NOR gates gives the S R Latch: Which has the time sequence S Time R behavior: 0 0
0 0 1 0 1 0
Chapter 5 - Part 1 44

R (reset)

S (set)

Q
Comment Stored state unknown Set Q to 1 Now Q remembers 1 Reset Q to 0 Now Q remembers 0 Both go low Unstable!

1 0 0 0 1 0

Q ? 1 1 0 0 0 ?

Q ? 0 0 1 1 0 ?

Clocked S - R Latch
Adding two NAND gates to the basic S - R NAND latch gives the clocked S R latch: S Q C Q R Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high. C means control or clock .

Chapter 5 - Part 1 45

Clocked S - R Latch (continued)

The Clocked S-R Latch can be described by a table:
S Q C Q R

Q(t) S 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 ??? 1 0 1 ???

Comme t No cha ge Clear Q Set Q I determi ate No cha ge Clear Q Set Q I determi ate

The table describes what happens after the clock [at time (t+1)] based on:
current inputs (S,R) and current state Q(t).
Chapter 5 - Part 1 46

D Latch
Adding an inverter to the S-R Latch, C gives the D Latch: Note that there are no indeterminate states! Q(t+1) Comment Q D
0 0 1 1 0 1 0 1 0 1 0 1
D Q

T e grap ic symbol for a D Latc is:

D C Q Q

No change Set Q Clear Q No Change

Chapter 5 - Part 1 47

S-R Master-Slave Flip-Flop

Consists of two clocked S S S Q Q Q S-R latches in series C C C with the clock on the R R Q R Q second latch inverted Q The input is observed by the first latch with C = 1 The output is changed by the second latch with C = 0 The path from input to output is broken by the difference in clocking values (C = 1 and C = 0). The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur.
Chapter 5 - Part 1 48

J-K Flip-flop
Behavior
Same as S-R flip-flop with J analogous to S and K analogous to R Except that J = K = 1 is allowed, and For J = K = 1, the flip-flop changes to the opposite state As a master-slave, has same 1s catching behavior as S-R flip-flop If the master changes to the wrong state, that state will be passed to the slave
E.g., if master falsely set by J = 1, K = 1 cannot reset it during the current clock cycle

Chapter 5 - Part 2 49

J-K Flip-flop (continued)

Implementation
To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop

 Symbol

J C K

J K

D C

Chapter 5 - Part 2 50

T Flip-flop
Behavior
Has a single input T
For T = 0, no change to state For T = 1, changes to opposite state

Same as a J-K flip-flop with J = K = T As a master-slave, has same 1s catching behavior as J-K flip-flop Cannot be initialized to a known state using the T input
Reset (asynchronous or synchronous) essential

Chapter 5 - Part 2 51

T Flip-flop (continued)
Implementation
To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop

 Symbol

C T D C

Chapter 5 - Part 2 52

Basic Flip-Flop Descriptors

Used in analysis
Characteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current state Characteristic equation - defines the next state of the flip-flop as a Boolean function of the flipflop inputs and the current state

Used in design
Excitation table - defines the flip-flop input variable values as function of the current state and next state
Chapter 5 - Part 2 53

D Flip-Flop Descriptors
Characteristic Table
D 0 1 0 1 Q(t 1) Operation Reset Set

Characteristic Equation Q(t+1) = D Excitation Table

Q(t 1) 0 1 D 0 1

Operation Reset Set

Chapter 5 - Part 2 54

T Flip-Flop Descriptors
Characteristic TableOperation T Q(t +1)
0 1 Q(t) Q(t) No change Complement

Characteristic Equation Q(t+1) = T Q Excitation Table

Q(t + 1) Q(t) Q(t) T 0 1 Operation No change Complement

Chapter 5 - Part 2 55

S-R Flip-Flop Descriptors

Characteristic Table
R Q(t +1) Operation 0 0 0 1 1 0 1 1 Q(t) 0 1 ? No change Reset Set Undefined

Characteristic Equation Q(t+1) = S + R Q, S.R = 0 Excitation Table

Q(t) Q(t+1) 0 0 1 1
Chapter 5 - Part 2 56

R Operation 0 X No change 1 0 Set 0 1 Reset X 0 No change

0 1 0 1

J-K Flip-Flop Descriptors

Characteristic Table
J K Q(t+1) 0 0 1 1 0 1 0 1 Q(t) 0 1 Q(t) Operation No change Reset Set Complement

Characteristic Equation Q(t+1) = J Q + K Q Excitation Table Q(t) Q(t + 1) J K

0 0 1 1
Chapter 5 - Part 2 57

Operation No change Set Reset No Change

0 1 0 1

0 1 X X

X X 1 0

Flip-flop Behavior Example

Use the characteristic tables to find the output waveforms for the flip-flops shown:
Clock D,T

D C

QD

T C

QT

Chapter 5 - Part 2 58

Flip-Flop Behavior Example (continued)

Use the characteristic tables to find the output waveforms for the flip-flops shown:
Clock S,J R,K
S C R J C K

QSR

QJK

Chapter 5 - Part 2 59

Registers
Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state table More often, think of a register as storing a vector of binary values Frequently used to perform simple data storage and data movement and processing operations
Chapter 7 - Part 1 60

Example: 2-bit Register

How many states are there? How many input combinations? Output combinations? What is the output function? What is the next state function? Current Moore or Mealy? State State Table:
A1 A0 0 0 0 1 1 0 1 1

A1 I 1 D Q C A0 I 0 CP D Q C

Y1

Y0

Next State A1(t+ 1) A0(t+ 1) For In1 In0 = 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

Output (=A1 A0) Y1 0 0 1 1 Y0 0 1 0 1

What are the quantities above for an n-bit register?

Chapter 7 - Part 1 61

Shift Registers
Shift Registers move data laterally within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this:
In DQ A DQ B DQ C DQ Out

CP

Data input, In, is called a serial input or the shift right input. Data output, Out, is often called the serial output. The vector (A, B, C, Out) is called the parallel output.

Chapter 7 - Part 1 62

Shift Registers (continued)

The behavior of the I serial shift register is given in the listing on the lower right T0 is the register Clock CP state just before CP the first clock pulse occurs T0 T1 T1 is after the first pulse and T2 before the second. T3 Initially unknown T4 states are denoted by ? T5 T6 Complete the last three rows of the table
Chapter 7 - Part 1 63

A DQ DQ

B DQ

C DQ

Out

In 0 1 1 0 1 1
1

A ? 0 1 1

B ? ? 0 1

C ? ? ? 0

Out ? ? ? ?

Parallel Load Shift Registers

DA DB By adding a mux A B between each shift register D D stage, data can be IN Q Q shifted or loaded If SHIFT is low, SHIFT A and B are CP replaced by the data on DA and DB lines, else data shifts right on each clock. By adding more bits, we can make n-bit parallel load shift registers. A parallel load shift register with an added hold operation that stores data unchanged is given in Figure 7-10 of the text.
Chapter 7 - Part 1 64

Shift Registers with Additional Functions

By placing a 4-input multiplexer in front of each D flip-flop in a shift register, we can implement a circuit with shifts right, shifts left, parallel load, hold. Shift registers can also be designed to shift more than a single bit position right or left Shift registers can be designed to shift a variable number of bit positions specified by a variable called a shift amount.

Chapter 7 - Part 1 65

Counters
Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: Ripple Counters
Clock connected to the flip-flop clock input on the LSB bit flip-flop For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous! Output change is delayed more for each bit toward the MSB. Resurgent because of low power consumption

Synchronous Counters
Clock is directly connected to the flip-flop clock inputs Logic is used to implement the desired state sequencing

Chapter 7 - Part 2 66

Ripple Counter
How does it work?
When there is a positive edge on the clock input of A, A complements The clock input for flipflop B is the complemented output of flip-flop A When flip A changes from 1 to 0, there is a positive edge on the CP clock input of B A causing B to complement B
Chapter 7 - Part 2 67

D Clock CR

D CR Reset

Ripple Counter (continued)

The arrows show the
cause-effect relation- CP ship from the prior A slide => The corresponding B sequence of states => 0 1 0 1 2 3 (B,A) = (0,0), (0,1), (1,0), behaves like bit Each additional bit, C, D, (1,1), (0,0), (0,1), B, changing half as frequently as the bit before it. For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0),
Chapter 7 - Part 2 68

Ripple Counter (continued)

These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flop s state. The changes ripple upward through the chain of flip-flops, i. e., each transition occurs after a clock-tooutput delay from the stage before. To see this effect in detail look at the waveforms on the next slide.

Chapter 7 - Part 2 69

Ripple Counter (continued)

Starting with C = B = A = 1, equivalent to (C,B,A) = 7 base 10, the next clock increments the count to (C,B,A) = 0 base 10. In fine timing detail:
The clock to output delay tPHL causes an increasing delay from clock edge for each stage transition. Thus, the count ripples from least to most significant bit. For n bits, total worst case delay is n tPHL.
tPHL
CP

tPHL
A

tpHL
B C

Chapter 7 - Part 2 70

Synchronous Counters
To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer =>
A3 A2 A1 A0

Incr m ter S3
S2 S1 S0

D3 Q3 D2 Q2 D1 Q1 D0 Q0

Clock

Chapter 7 - Part 2 71

Synchronous Counters (continued)

Internal details => Internal Logic
Incrementer
Count enable EN
D C Q0

XOR complements each bit AND chain causes complement of a bit if all bits toward LSB from it equal 1

D C

Q1

Count Enable
Forces all outputs of AND chain to 0 to hold the state
D
C Q2

Carry Out
Added as part of incrementer Connect to Count Enable of additional 4-bit counters to form larger counters
Clo
Chapter 7 - Part 2 72

D C

Q3

. Carry out ut CO a Logi Diagr m-Serial Gating

Synchronous Counters (continued)

Q0

Carry chain
series of AND gates through which the carry ripples Yields long path delays Called serial gating

EN Q1
1

Q2
2

Replace AND carry chain with ANDs => in parallel

Reduces path delays Called parallel gating Like carry lookahead Lookahead can be used on COs and ENs to prevent long paths in large counters

Q3
TR 4 EN Q0 Q1 Q2 Q3 O
3

O Logi Diagram-Parallel ating

Symbol for Synchronous Counter

Chapter 7 - Part 2 73

Symbol

Other Counters
See text for:
Down Counter - counts downward instead of upward Up-Down Counter - counts up or down depending on value a control
input such as Up/Down

Parallel Load Counter - Has parallel load of values available depending

on control input such as Load

Divide-by-n (Modulo n) Counter

Count is remainder of division by n; n may not be a power of 2 or Count is arbitrary sequence of n states specifically designed state-by-state Includes modulo 10 which is the BCD counter

Chapter 7 - Part 2 74

Counter with Parallel Load

Load

Add path for input data

enabled for Load = 1

Count D0 D C Q0

Add logic to:

disable count logic for Load = 1 disable feedback from outputs for Load = 1 enable count logic for Load = 0 and Count = 1
D1 D C Q1

The resulting function table: Loa Count Action 0 0 1

Chapter 7 - Part 2 75

D2

D C

Q2

0 1 X

Hol Store Value Count Up Store Value Loa D

Clock D3 D C Q3

Carry Output CO

Design Example: Synchronous BCD

Use the sequential logic model to design a synchronous
BCD counter with D flip-flops State Table => Current State Input combinations Q8 Q4 Q2 Q1 0 0 0 0 1010 through 1111 0 0 0 1 are don t cares
0 0 0 0 0 0 1 1
Chapter 7 - Part 2 76

0 0 1 1 1 1 0 0

1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1

Next State Q8 Q4 Q2 Q1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0

Synchronous BCD (continued)

Use K-Maps to two-level optimize the next state equations
and manipulate into forms containing XOR gates: D1 = Q1 D2 = Q2 + Q1Q8 D4 = Q4 + Q1Q2 D8 = Q8 + (Q1Q8 + Q1Q2Q4)

The logic diagram can be draw from these equations

An asynchronous or synchronous reset should be added

What happens if the counter is perturbed by a power

disturbance or other interference and it enters a state other than 0000 through 1001?

Chapter 7 - Part 2 77

Synchronous BCD (continued)

Find the actual values of the six next states for the don t care combinations from the equations Find the overall state diagram to assess behavior for the don t care states (states in decimal) 0 Present State Next State 9 1 14 Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1
1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1
Chapter 7 - Part 2 78

0 1 0 1 0 1

1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 0 1 0

8 15 7 6 5 11 13 10 4 12

2 3

Synchronous BCD (continued)

For the BCD counter design, if an invalid state is entered, return to a valid state occurs within two clock cycles Is this adequate? If not:
Is a signal needed that indicates that an invalid state has been entered? What is the equation for such a signal? Does the design need to be modified to return from an invalid state to a valid state in one clock cycle? Does the design need to be modified to return from a invalid state to a specific state (such as 0)?

The action to be taken depends on:

the application of the circuit design group policy See pages 244 of the text.
Chapter 7 - Part 2 79

Memory Definitions
Memory A collection of storage cells together with the necessary circuits to transfer information to and from them. Memory Organization the basic architectural structure of a memory in terms of how data is accessed. Random Access Memory (RAM) a memory organized such that data can be transferred to or from any cell (or collection of cells) in a time that is not dependent upon the particular cell selected. Memory Address A vector of bits that identifies a particular memory element (or collection of elements).

Chapter 8 80

Memory Definitions (Continued)

Typical data elements are:
bit a single binary digit byte a collection of eight bits accessed together word a collection of binary bits whose size is a typical unit of access for the memory. It is typically a power of two multiple of bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)

Memory Data a bit or a collection of bits to be stored into or accessed from memory cells. Memory Operations operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc.).
Chapter 8 81

Memory Block Diagram

D ta I ut Li es A basic memory system is n shown here: k address lines are Memory k A ress Li es Unit decoded to address 2k k 2k Words words of memory. n Bits per Word 1 Read Each word is n bits. 1 Write Read and Write are single control lines defining the n simplest of memory n Data Output Lines operations.
Chapter 8 82

Memory Organization Example

Example memory contents:
A memory with 3 address bits & 8 data bits has: k = 3 and n = 8 so 23 = 8 addresses labeled 0 to 7. 23 = 8 words of 8-bit data
Chapter 8 83

Memory Address Binary Decimal

000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7

Memory Content
10001111 11111111 10110001 00000000 10111001 10000110 00110011 11001100

Basic Memory Operations

Memory operations require the following:
Data data written to, or read from, memory as required by the operation. Address specifies the memory location to operate on. The address lines carry this information into the memory. Typically: n bits specify locations of 2n words. An operation Information sent to the memory and interpreted as control information which specifies the type of operation to be performed. Typical operations are READ and WRITE. Others are READ followed by WRITE and a variety of operations associated with delivering blocks of data. Operation signals may also specify timing info.
Chapter 8 84

Basic Memory Operations (continued)

Read Memory an operation that reads a data value stored in memory:
Place a valid address on the address lines. Wait for the read data to become stable.

Write Memory memory:

an operation that writes a data value to

Place a valid address on the address lines and valid data on the data lines. Toggle the memory write control line

Sometimes the read or write enable line is defined as a clock with precise timing information (e.g. Read Clock, Write Strobe).
Otherwise, it is just an interface signal. Sometimes memory must acknowledge that it has completed the operation.
Chapter 8 85

Memory Operation Timing

Most basic memories are asynchronous
Storage in latches or storage of electrical charge No clock

Controlled by control inputs and address Timing of signal changes and data observation is critical to the operation Read timing:
Clock Address Memory enable Read/ Write Data output 65 ns
Chapter 8 86

20 ns T1

T2

T3 Address valid

T4

T1

Data valid

Read cycle

Memory Operation Timing

Write timing:
20 ns Clock Address Memory enable Read/ Write Data input Data valid T1 T2 T3 Address valid T4 T1

75 ns Critical times measured with respect to edges of write pulse (1-0-1): Write cycle

Address must be established at least a specified time before 1-0 and held for at least a specified time after 0-1 to avoid disturbing stored contents of other addresses Data must be established at least a specified time before 0-1 and held for at least a specified time after 0-1 to write correctly

Chapter 8 87

RAM Integrated Circuits

Types of random access memory
Static information stored in latches Dynamic information stored as electrical charges on capacitors
Charge leaks off Periodic refresh of charge required

Dependence on Power Supply

Volatile loses stored information when power turned off Non-volatile retains information when power turned off

Chapter 8 88

Static RAM
SR Latch Select input for control Dual Rail Data Inputs B and B Dual Rail Data Outputs C and C

Cell

Array of storage cells used to implement static RAM Select Storage Cell
B C

Q RAM cell

Chapter 8 89

Making Larger Memories

Using the CS lines, we can make larger memories from smaller ones by tying all address, data, and R/W lines in parallel, and using the decoded higher order address bits to control CS. Using the 4-Word by 1Bit memory from before, we construct a 16-WordA3 by A2 A1 1-Bit memory.
Chapter 8 90

Data I Decoder
D3
A1 D-I A0 R/W CS D-Out A1 D-I A0 R/W CS D-Out A1 D-I A0 R/W CS D-Out A1 D-I A0 R/W CS D-Out

D2

D1

S1 D0 S0

Data Out

A0 R/W

Making Wider Memories

To construct wider memories from narrow ones, we tie the address and control lines in parallel and keep the data lines separate. For example, to make a 4word by 4-bit memory from 4, 4-word by 1-bit memories Note: Both 16x1 and 4x4 A1 A0 memories take 4-chips and hold 16 bits of data. R/W
CS
Chapter 8 91

Data I
A1 D-I A0 R/W CS D-Out A1 D-I A0 R/W CS D-Out A1 D-I A0 R/W CS D-Out A1 D-I A0 R/W CS D-Out

3210

Data Out

3210

Dynamic RAM (DRAM)

Basic Principle: Storage of information on capacitors. Charge and discharge of capacitor to change stored value Use of transistor as switch to:
Store charge Charge or discharge

See next slide for circuit, hydraulic analogy, and logical model.
Chapter 8 92

Dynamic RAM (continued)

Select T C DRAM cell (a) Select (b) (c) To Pump

Stored 1

Stored 0

Write 1
(d) (e)

Write 0

D C

Q DRAM cell model (h)

Read 1

Read 0

(f)

(g)

Chapter 8 93

Dynamic RAM Rea Timing

20 ns Clock T1 Row Address T2 Column Address T3 T4 T1

Address

RAS

CAS

Output enable Rea / Write

Data output

Hi-Z 65 ns Rea cycle

Data vali

Chapter 8 94

DRAM Types
 Types to be discussed
Sync ronous DRAM (SDRAM) Double Data Rate SDRAM (DDR SDRAM) RAMBUS DRAM (RDRAM)

 Justification for effectiveness of t ese types

DRAM often used as a part of a memory ierarc y (See details in c apter 14) Reads from DRAM bring data into lower levels of t e ierarc y Transfers from DRAM involve multiple consecutively addressed words Many words are internally read wit in t e DRAM ICs using a single row address and captured wit in t e memory T is read involves a fairly long delay

Chapter 8 95

DRAM Types (continued)

 Justification for effectiveness of t ese types (continued)
T ese words are t en transferred out over t e memory data bus using a series of clocked transfers T ese transfers ave a low delay, so several can be done in a s ort time T e column address is captured and used by a sync ronous counter wit in t e DRAM to provide consecutive column addresses for t e transfers

 burst read t e resulting multiple word read from consecutive addresses

Chapter 8 96