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S.Chandra Srinivas
Sekhar 1250210108
18/7/2011
INTRODUCTION
Here we will consider general off-line BIST structures that are applicable to chips and boards consisting of blocks of combinational logic interconnected by storage cells
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Test pattern generators (TPG) Output response analyzers (ORA) The circuit under test (CUT) The distribution system (DIST) The BIST controller
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Off-line BIST architecture at the chip level and board level can be classified according to the following criteria
Generic form of distributed and separate BIST architectures Here each cut is associated with its own TPG and ORA circuitary These leads to more overhead but less test time Accurate diagnosis
DIGITAL SYSTEM TESTING AND TESTABLE DESIGN
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Here TPG and ORA elements are configured from functional elements with in the CUT, such as registers Advantage : This leads to more complex design to control and
DIGITAL SYSTEM TESTING AND TESTABLE DESIGN
The choice of BIST architecture is a function of several factors , some of which are listed below .
Degree of test parallelism Fault coverage Levels of packaging Test time Physical constraints Complexity of replaceable units Factory and field test and repair strategy Performance degradation
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Centralized and Sepreate Board level BIST architecture (CSBL) Built in Evaluation and Self Test architecture (BEST)
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Centralized and Separate BIST architecture No boundary scan Combinational or Sequential CUT
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DIGITALSYSTEM TESTING AND TESTABLE DESIGN
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The built in evaluation and self test architecture is an application of the CSBL design to chips
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In General logic being tested is a sequential circuit The inputs to the CUT are driven my a PRPG and the outputs are compressed using a MISR Either a MUX can be used or PIs can be loaded into the PRPG and then loaded into the CUT . The same concept applied to the output Both Embedded and Separate version of architecture exists
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Embedded : PIs and POs to the CUT go directly to registers and driven by registers
Here the BIST architecture results in low fault coverage because they are based on the testing sequential circuits
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CONCLUSION
To over come this problem an internal scan path can be used with in the CUT
So that the testing of CUT can be reduced to the problem of testing the combinational logic.
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THANK YOU
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