EE 5301 – VLSI Design Automation I

Part I: Introduction

Kia Bazargan

University of Minnesota

Fall 2006 EE 5301 - VLSI Design Automation I I-1

 What is This Course All About?
• Prerequisite
 C / C++ programming experience
 Kia will try to provide tutorials
• What is covered?
 Basic algorithms, complexity theory
 Integrated circuit (IC) Design flow
 Computer Aided Design (CAD) tool development for
Very Large Scale Integration (VLSI)
 Lots of programming!
• Next slides:
 Overview of IC design steps
 Related courses at U of M
 Outline of this course
Fall 2006 EE 5301 - VLSI Design Automation I I-2
 IC Products
• Processors
 CPU, DSP, Controllers
• Memory chips
 RAM, ROM, EEPROM
• Analog
 Mobile communication,
audio/video processing
• Programmable
 PLA, FPGA
• Embedded systems
 Used in cars, factories
 Network cards Skip
• System-on-chip (SoC) econ
Images: amazon.com

Fall 2006 EE 5301 - VLSI Design Automation I I-3

 More Demand for EDA

CAE = Computer Aided Engineering

Source: http://www.edat.com/edac
Fall 2006 EE 5301 - VLSI Design Automation I I-4
 Example: Intel Processor Sizes
Silicon Process 1.5 1.0 0.8 0.6 0.35 0.25
Technology
Intel386TM DX
Processor

Intel486TM DX
Processor

Pentium® Processor

Pentium® Pro &

Pentium® II Processors
Source: http://www.intel.com/
Fall 2006 EE 5301 - VLSI Design Automation I I-5
 Increasing Device and Context Complexity
• Exponential increase in device
complexity
 Increasing with Moore's law (or faster)!

Complexity
• More complex system contexts
 System contexts in which devices are
deployed (e.g. cellular radio) are increasing
in complexity
• Require exponential increases in design
productivity

We
Wehave
haveexponentially
exponentiallymore
moretransistors!
transistors!

Fall 2006 EE 5301 - VLSI Design Automation I [©Keutzer] I-6

 Deep Submicron(DSM) Effects
• Smaller geometries are causing a wide
variety of effects that we have largely

DSM Effects
ignored in the past:
 Cross­coupled capacitances
 Signal integrity
 Resistance
 Inductance

Design
Designof
ofeach
eachtransistor
transistoris
isgetting
gettingmore
moredifficult!
difficult!

Fall 2006 EE 5301 - VLSI Design Automation I [©Keutzer] I-7

 Heterogeneity on Chip
• Greater diversity of on­chip
elements
 Processors
 Software
Heterogeneity
 Memory
 Analog
 APU’s ?

More
Moretransistors
transistorsdoing
doingdifferent
differentthings!
things!

Fall 2006 EE 5301 - VLSI Design Automation I [©Keutzer] I-8

 Stronger Market Pressures
• Decreasing design window
• Less tolerance for design
revisions
Time-to-market

Exponentially
Exponentiallymore
morecomplex,
complex,greater
greaterdesign
designrisk,
risk,
greater
greatervariety,
variety,and
andaasmaller
smallerdesign
designwindow!
window!

Fall 2006 EE 5301 - VLSI Design Automation I [©Keutzer] I-9

 A Quadruple­Whammy

Complexity
Time-to-market Heterogeneity

DSM Effects

Fall 2006 EE 5301 - VLSI Design Automation I [©Keutzer] I-10

 IC Design Steps (cont.)
High-level
High-level Functional
Functional
Specifications
Specifications Description
Description Description
Description

Behavioral Structural
VHDL, C VHDL

Fall 2006 EE 5301 - VLSI Design Automation I Figs. [©Sherwani] I-11

 IC Design Steps (cont.)
High-level
High-level Functional
Functional
Specifications
Specifications Description
Description Description
Description

Synthesis
Physical Technology
Design Mapping
Placed
Placed Logic
&& Routed Gate-level
Gate-level Logic
Routed Design Description
Description
Design
Design Design

Packaging Fabri- X=(AB*CD)+

cation (A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))

Fall 2006 EE 5301 - VLSI Design Automation I Figs. [©Sherwani] I-12

 The Big Picture: IC Design Methods
Design Cost / Quality # Companies
Methods Development involved
Time
Full Custom

Standard Cell
Library Design

ASIC – Standard
Cell Design

RTL-Level Design

Fall 2006 EE 5301 - VLSI Design Automation I I-13

 Optimization: Levels of Abstraction
• Algorithmic
 Encoding data, computation
scheduling, balancing delays of
components, etc.

Effectiveness
• Gate-level

Level of detail
 Reduce fan-out, capacitance
 Gate duplication, buffer insertion
• Layout / Physical-Design
 Move cells/gates around to
shorten wires on critical paths
 Abut rows to share power /
ground lines

Fall 2006 EE 5301 - VLSI Design Automation I I-14

 Full Custom Design
Structural/RTL Description Component Design
Ctrl

Mem Reg Comp.

File Unit

Place & Route

comp
PLA

I/O

RAM
...
A/D
Floorplan [©Sherwani]
Layouts [© Prentice Hall]
Fall 2006 EE 5301 - VLSI Design Automation I I-15
 Full Custom Design Example
I/O Pad
Via

comp
Metal2
PLA I/O
Metal1
Macro
cell RAM
design
Glue logic
(standard
A/D cell design)

[©Sherwani]
Fall 2006 EE 5301 - VLSI Design Automation I I-16
 The chip is organized in clusters, clusters
consist of units, and units are composed
of functional blocks (in short, blocks).

The process of automating a full-custom

design style has a much higher
complexity than other restricted models.
A macrocell array is an approach to the design and manufacture of
ASICs. Essentially, it is a small step up from the otherwise similar
gate array, but rather than being a prefabricated array of simple
logic gates, the macrocell array is a prefabricated array of higher-
level logic functions such as flip-flops, ALU functions, registers,
and the like.

Fall 2006 EE 5301 - VLSI Design Automation I I-17

 ASIC Design
Structural/ HDL Programming
RTL Description
P_Inp: process (Reset, Clock)
Ctrl begin
if (Reset = '1') then
sum <= ( others => '0' );
input_nums_read <= '0';
Reg Comp. sum_ready <= '0';
Mem
File Unit
add82 : kadd8 port map (
a => add_i1, b => add_i2,
ci => carry, s => sum_o);
Mult_i1 <= sum_o(7 downto 0);

D C C B

A C C

D C D B
Cell library
C C C B
A B
C D
Floorplan [©Sherwani]
Fall 2006 EE 5301 - VLSI Design Automation I I-18
 ASIC (Standard Cell) Design Example
VDD Metal1 Cell GND
Metal2

D C C B

A C C
Cell library
A B
D C D B
C D

C C C B

Placement [©Sherwani]
Fall 2006 EE 5301 - VLSI Design Automation I I-19
 Where Is This Course in the Big Picture?
• VLSI related courses:
VLSI CAD VLSI Design Others

EE 5301 EE 4301
VLSI Design
EE 5323 Digital Design
VLSI Design I With Programmable
Automation I
Logic

EE 5302 EE 5324 EE 5329

VLSI Design VLSI Design II
VLSI Digital
Automation II
Signal Processing
Systems

EE 5333 EE 5549
Analog Digital
Integrated Circuit Signal Processing
Design Structures for VLSI

Fall 2006 EE 5301 - VLSI Design Automation I I-20

 Course Outline
• Basic algorithms and complexity theory
 Circuit representations
 Classes of problems (P, NP)
 Classes of algorithms (dynamic programming, network
flow, greedy, linear programming, etc.)
 Graph algorithms
• High-level synthesis
 Converting high-level languages to RTL
 Scheduling operations
 Allocating functional resources (adders, multipliers,
registers, etc.)
 Register minimization

Fall 2006 EE 5301 - VLSI Design Automation I I-21

 Course Outline (cont.)
• Partitioning
 FM, KL, hMetis algorithms
• Floorplanning
 Slicing, non-slicing floorplans
 Simulated annealing floorplanning algorithms
• Placement / Packing
 Force-directed
 Simulated annealing
 Quadratic placement
• Global / detailed routing
 Maze routing, line-search, Steiner trees, channel
routing,
Fall 2006 EE 5301 - VLSI Design Automation I I-22