DMA

DMA Definitions:

 DMA occurs between an I/O device and memory without the

use of the microprocessor

 DMA read transfer data from the memory to I/O device

 DMA write transfer data from the I/O to memory

 MRDC & IOWC signals to simultaneously activate for read

DMA

 DMA write signals MWTC & IORC

 DMA controller provides the memory with its address and a

signals from the controller DACK selects the I/O device, during
the DMA transfer

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Basic DMA operation:

The direct memory access (DMA) I/O technique provides direct

access to the memory while the microprocessor is temporarily
disabled.

 A DMA controller temporarily borrows the address bus, data

bus, and control bus from the microprocessor and transfers the
data bytes directly between an I/O port and a series of memory
locations.

 The DMA transfer is also used to do high-speed memory-to

memory transfers.

 Two control signals are used to request and acknowledge a DMA

transfer in the microprocessor-based system.

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Basic DMA operation :

 The HOLD signal is a bus request signal which asks the

microprocessor to release control of the buses after the current
bus cycle.

 The HLDA signal is a bus grant signal which indicates that the
microprocessor has indeed released control of its buses by
placing the buses at their high-impedance states.

 The HOLD input has a higher priority than the INTR or NMI
interrupt inputs.

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Example: memory-to-device transfer

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The 8237 DMA controller:

 The 8237 DMA controller supplies the memory and I/O with
control signals and memory address information during the DMA
transfer.

 The 8237 is a four-channel device that is compatible to the

8086/8088 microprocessors and can be expanded to include any
number of DMA channel inputs.

 The 8237 is capable of DMA transfers at rates of up to 1.6M bytes

per second.

 Each channel is capable of addressing a full 64K-byte section of

memory and can transfer up to 64K bytes with a single
programming.

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Some important signal pins:

‡ DREQ3 ± DREQ0 (DMA request): Used to

request a DMA transfer for a particular DMA
channel.

‡ DACK3 ± DACK0 (DMA channel

acknowledge): Acknowledges a channel
DMA request from a device.

‡ HRQ (Hold request): Requests a DMA

transfer.

‡ HLDA (Hold acknowledge) signals the

8237 that the microprocessor has
relinquished control of the address, data
and control buses.

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Some important signal pins:

‡ AEN (Address enable): Enables the DMA

address latch connected to the 8237 and
disable any buffers in the system connected
to the microprocessor. (Use to take the
control of the address bus from the
microprocessor)

 ADSTB (Address strobe): Functions as ALE

to latch address during the DMA transfer.

‡ EOP (End of process): bi direction, Signals

the end of the DMA process.

‡ IOR (I/O read): bi-dir, Used as an input

strobe to read data from the 8237 during
programming and used as an output strobe
to read data from the port during a DMA write
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 DMA

Some important signal pins:

 IOW (I/O write): bi-dir Used as an input

strobe to write data to the 8237 during
programming and used as an output strobe
to write data to the port during a DMA read
cycle.

 MEMW (Memory write): Used as an output

to cause memory to write data during a
DMA write cycle.

 MEMR (Memory read): Used as an output

to cause memory to read data during a DMA
read cycle

 A3 ± A0 : address pins select an internal

register during programming and provide
part of the DMA transfer address during
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DMA operation.
 DMA

Some important signal pins:

 A7 ± A4 : address pins are outputs that

provide part of the DMA transfer address
during a DMA operation.

 DB0 ± DB7 : data bus, connected to

microprocessor and are used during the
programming DMA controller.

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Internal registers:

‡ CAR : The m






 is used to hold the 16-bit
memory address used for the DMA transfer.

‡ CWCR : The m


m 



 programs a channel for
the number of bytes (up to 64K) transferred during a DMA action.

‡ BA & BWC : The 
 and 
m registers

are used when auto-initialization is selected for a channel. In this
mode, their contents will be reloaded to the CAR and CWCR after
the DMA action is completed.

‡ The m 


(CR) programs the operation of the
8237 DMA controller

‡ Each channel has its own CAR, CWCR, BA and BWC.

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‡ MR : The  


 programs the mode of operation for a
channel. Each channels has its own mode register

‡ RR : The
 



 is used to request a DMA transfer
via software, which is very useful in memory-to-memory
Transfers where external signals is not available for DMA transfer

‡ MRSR : The 




 sets or clears the channel
mask to disable or enable particular DMA channels. If the mask is set,
The channel is disabled

‡ MSR : The 



 clears or sets all of the masks with
one command instead of individual channels as with the
MRSR.

‡ SR : The  



 shows the status of each DMA channel. TC
Bits indicate, terminal count

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8237A-5 Command register 8237A-5 Mode register

h h




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8237A-5 Request register
8237A-5 mask set / reset register

8237A-5 Mask register 8237A-5 Status register

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 DMA

Data Transfer modesá

Single Transfer Mode

 In Single Transfer mode the device is programmed to make one
transfer only.

 The word count will be decremented and the address

decremented or incremented following each transfer.

 When the word count ``rolls over'' from zero to FFFFH, a

Terminal Count (TC) will cause an Auto initialize if the channel
has been programmed to do so.

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Block Transfer Mode

 In Block Transfer mode the device is activated by DREQ to

continue making transfers during the service until a TC, caused
by word count going to FFFFH, or an external End of Process
(EOP) is encountered.

 DREQ need only be held active until DACK becomes active.

Again, an Autoinitialization will occur at the end of the service
if the channel has been programmed for it.

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Demand Transfer Mode:

 In Demand Transfer mode the device is programmed to continue
making transfers until a TC or external EOP is encountered or until
DREQ goes inactive.

 Transfers may continue until the I/O device has exhausted its data
capacity. the DMA service can be re-established by means of a DREQ.

 During the time between services when the microprocessor is

allowed to operate, the intermediate values of address and word count
are stored in the 8237A Current Address and Current Word Count
registers.

 EOP can cause an Autoinitialize at the end of the service. EOP is

generated either by TC or by an external signal.

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Cascade Mode:
 more than one 8237A
together for simple system
expansion.

The HRQ and HLDA signals

from the additional 8237A are
connected to the DREQ and
DACK signals of a channel of
the initial 8237A.

This allows the DMA requests

of the additional device to
propagate through the priority
network circuitry of the
preceding device.

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Software Command:
 There are 3 software commands used to control the operation
of the 8237.

 These commands do not have a binary bit pattern,

 A simple output to the correct port number enables the software

command.

Software commands,
 Clear the first/last f/f : clear the first/last f/f within the 8237.
if F/L = 0, the low order byte is selected for read/write in the
current address & current count register.
if F/L = 1, the high order byte is selected for read/write in the
current address & current count register.

 Master clear : acts same as RESET signal to the 8237, this command
disables all channels

- Clear mask register : Enables all 4 DMA channels.

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8237A ± 5 Command & control port assignment

ignals peration
A3 A2 A A
ead stat s register
rite command
llegal
rite re est register
llegal
rite single mas
llegal
rite mode register
llegal
Clear te pointer
ead temporar
M aster clear
llegal
Clear mas register
llegal
rite all mas register

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Programming the 8237:

the state of the F/L f/f determines whether the LSB or MSB
Is programmed

if the state of the F/L f/f is unknown, the count and address
Could be programmed incorrectly

disable the DMA channel before programming the count &

address

There are 4 steps required to program the address and

count registers first:
1. Clear the F/L flip-flop with a clear F/L command
2. Disable the channel
3. Program the LSB and then MSB of the address
4. Program the LSB and then MSB of the count

 Additional programming is required to select the mode of

operation before the channel is enabled and started.
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Programming the address & count register
e r a tio n sig n a s n te r n a a ta u s
h a n n e e g iste r

a se & u rre n t a d d r r ite

u rre n t a d d r re a d

a se & u rre n t o rd r ite

u rre n t o rd re a d

a se & u rre n t a d d r r ite

u rre n t a d d r re a d

a se & u rre n t o rd r ite

u rre n t o rd re a d

a se & u rre n t a d d r r ite

u rre n t a d d r re a d

a se & u rre n t o rd r ite

u rre n t o rd re a d

a se & u rre n t a d d r r ite

u rre n t a d d r re a d

a se & u rre n t o rd r ite

u rre n t o rd re a d

2
 
 
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DMA- Processed Printer Interface:

 ACK indicates printer needs data -- also used as a DMA request.

 DACK3 latches data in '373 Latch and generates DS to printer

through the single shot '122.

 Once programmed with address of data and # of chars, the

8237 transfers a byte at a time.

 Note that the I/O device is NOT selected by decoding the

address bus, but rather by DACK, since address bus contains a
memory address.

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 ACK is used to request a DMA action through a flip-flop

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Shared Bus Operation:

 A  

m
 system (also called distributed system) uses
more than one microprocessor to accomplish the work.

 A  

 system performs more than one task at a time.

 In a distributed, multiprocessing, multitasking environment,each

microprocessor accesses two buses: (1) the local bus and (2) the
remote or shared bus.

 The  m is connected to memory and I/O devices that are
directly accessed by a single microprocessor without any special
protocol or access rules.

 The 
 contains memory and I/O that are accessed by

any microprocessor in the system.

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Local Local Local Local Local Local

memory I/O memory I/O memory I/O

Local bus Local bus Local bus

Bus slave Bus slave Bus slave

Microprocessor Microprocessor Microprocessor

Shared bus
Bus master
Microprocessor

Shared Shared
memory I/O

A block diagram , the local & shared buses

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 Characteristics of buses:
Local bus-
- Resident to the microprocessor
- Contains the resident or local memory and I/O
Shared bus-
- Is connected to all microprocessors in the system
- Is used to exchange data between microprocessors in
the system
Î The shared bus in the personal computer is what we often
call the local bus in the personal computer as it is local to the
microprocessor in the personal computer.
‡ A  
is a device (microprocessor or otherwise) that
can control a bus containing memory and I/Ov

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 A remote bus master microprocessor can execute variable
software but the DMA controller can only transfer data.
‡ Access to the shared bus for the remote bus master is
accomplished via a bus arbiter.
‡ A  


functions to resolve priority between bus
masters and allows only one device at a time to access the
shared bus.

Bus Arbiter:

R The 8289 bus arbiter controls the interface of a bus master to

a shared bus.

 The 8289 is designed to function with the 8086/8088

microprocessors.

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X5V GND

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S2 
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S1
S0  |

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 DMA
Definition of some pins

‡ Ä
 m mused to synchronize all shared-bus

masters.

‡ Ä 




allows the 8289 to acquire the shared
bus on the next falling edge of the Ä
signal.

‡ Ä 



 used to resolve priority in a system
that contains multiple bus masters.

‡ Ä 
 used to request access to the shared

bus

‡ Ä
 
 indicates that an 8289 has acquired the
shared bus when used as an output , or used to detect that
another 8289 has acquired the shared bus when used as an
input.

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‡ Äm   
 a lower priority microprocessor is

asking for the use of the shared bus.

‡ Äselects, when 
Ä=1, whether the 8289 operates iV a
shared-bus system with I/O (=0) or with memory and I/O (==1)

‡ 
Ä

 configure the 8289 as a shared-bus master
(=1) or a local-bus master (=0).

‡

Ä/ 
Ä 

selects the shared-bus
(=1) or the resident local bus (=0)

 S2,S1,s0 ( status i/p) : initiate shared bus request & surrenders.

This are connected to the 8288 system bus controller status pins

 AEN ( address enable ) : o/p causes the bus drivers in a system to

switch to their three-state, high-impedance state
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‡ CRQLCK ( common request lock ) : i/p prevents 8289 from

surrendering the shared bus to any 8289s

 INIT ( initialization) : i/p resets the 8289 and is normally connected

to the system RESET signal

 LOCK : i/p prevents the 8289 from allowing any microprocessor

from gaining access to shared bus

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General 8289 operation

Three basic operation modes of an 8289:

1. I/O peripheral bus mode: All devices on the local bus are
treated as I/O, including memory, and are accessed by I/O
instructions. The shared bus is accessed by memory access.

2. Resident bus mode: Allows memory and I/O accesses on both

the local and shared bus.

3. Single-bus mode: Cannot access local memory and local I/O

Mode Pin Connections

Single bus IOB = 1 & RESB = 0
Resident bus IOB = 1 & RESB = 1
I/O Bus IOB = 0 & RESB = 0
I/O bus & resident bus IOB = 0 & RESB = 1
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 The 8288 is used as a bus controller when the 8088 operates in

MAX mode.

‡ The shared bus is only to pass information from one processor

to another.

 The bus masters function in their own local bus modes using
their own local programs, memory, and I/O space.

‡ Microprocessors connected in a system like this is called


or 


 
m
as they can execute software in
parallel.

 The shared bus is mapped to some particular address locations

such that accessing these address locations implies accessing
the shared bus.

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 The address decoder can detect the intention of accessing the

shared bus and then activates the corresponding 8288 and
configures the 8289 via 8289's 
Äinput pin.

‡ Blocking occurs whenever another microprocessor is accessing

the shared bus.

‡ The 8289 controls the shared bus by making the READY input
to the microprocessor be 0 if access to the shared bus is denied.

‡ Wait states are added until READY is 1.

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Priority Logic using the 8289:

 Only one can access the shared bus at a time.

 Two methods can be used to solve the priority:

- daisy-chain priority
- parallel-priority
Daisy-chain priority:




BUSY CBRQ BUSY CBRQ BUSY CBRQ

8289 8289 8289
BPRN BPRO BPRN BPRO BPRN BPRO
 

       

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 If no requests are active, all Äinputs will see 0.

‡ When an 8289 initiates a request, as soon as it receives a bus

acknowledgement, its Äbecomes 1 and blocks all lower
priority 8289s.

‡ Potential problem arise when more than 1 microprocessor

access the shared bus at a time.

‡ It's use is limited to no more than 3 8289s in a system that uses

a bus clock of less than 10 MHz

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Parallel Priority:

       

BUSY CBRQ BUSY CBRQ BUSY CBRQ BUSY CBRQ

8289 8289 8289 8289
BPRN BPRO BPRN BPRO BPRN BPRO BPRN BPRO

V   V
 





 

u u  
 priority 

 encoder  
  V 



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 If all 8289 arbiters are idle (SYSB/

Ä=0), the highest priority
8289 will gain access to the shared bus if it is requested by its
microprocessor.

‡ If a lower priority request is made,

- The Äoutput becomes 0, which causes the priority

encoder to place a 0 on the corresponding 8289's Äinput
and allows access to the shared bus.

- The Ä
signal becomes 0 and locks out any other
request.

‡ If simultaneous requests occur, the 74LS148 automatically

resolves the priority to prevent conflicts

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Disk Memory System:

Magnetic and optical:

 Floppy disks
 Hard disks
 CD-ROMs and WORMs (write once/read mostly)
 DVD
Floppy Disk Memory:

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 Older 5 and 1/4 flexible floppies spin at 300 RPM, have 40 tracks with
9 sectors/track and two sides.

 Capacity = 40 r2 r9 r512 = 368,640 or ~360K bytes of information.

 Newer ones are high-density with 80 tracks and 15 sector/track for

1.2 MB.

 The recording format called MFM (modified frequency modulation)

used to write double density format.

 The rules are given as follows:

- A data pulse is always stored for a logic 1.

No data and no clock is stored for the first logic 0 in a string of
logic 0s.
The second and subsequent logic 0s in a row contain
a clock pulse, but no data pulse.
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 The clock is inserted in subsequent 0s to maintain synchronization as

data is read from the diskv

$ %
 &
'"

Write protect

Head door

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 Advantages of the micro-floppy over the mini-floppy.

´Rigid plastic case provided better protection.

´Head door kept disk from being exposed.
´Write protection mechanism.
´Keyed mechanism for track 0.
´Increase in storage capacity

 80 tracks r2 sides r18 sectors/track r512 bytes/sector = 1.44

MB.

 Extended high density micro-floppy capable of 2.88 MB.

 A second extension is the floptical disk which stores data

magnetically using an optical tracking system. It stores 21 MB
of data.

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Hard Disk Memory:

 Use a flying head to store and read data from the platters and
spins at 3,000 to 10,000 RPM (> 10X that of floppies).

 Hard disks usually have at least 4 platters and can have 2 heads
per surface.

 The heads are moved from cylinder to cylinder using a voice coil.

 Hard disks use MFM or RLL (run-length limited) to store information.

 RLL 2,7 is common today -- this indicates that the number of

zeros in a row is always between 2 and 7.

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 The data is first encoded using the

table given below.

 Note that this encoding always

guarantees at least 2 [
and no
more than 7 [
in a row.

This encoding allows nearly a ß


increase in storage capacity over
MFMs without changing the driver
electronics or disk surface.
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 DMA

 RLL drives increase the number of tracks from 18 to 27 to

achieve this.

 40 MB -> 60 MB with better performance.

For example, given the data stream 101001011:

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 Although all disks use MFM or RLL, disk interfaces vary.

 Today's systems use 

(non-existent),

(small
computer system interface) and (integrated drive
electronics).

 IDE incorporates the disk controller in the disk drive and

usually contain a 32 KB cache.

 Access times are less than 10ms (compared with 200ms for
floppies).

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Optical Disk Memory:

 CD-ROMs and WORMs ( write once/read memory) store up
to 660 MB of data.

 DVDs are similar but have much higher bit density (4.7, 8.5
and 17 GB).

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Video Displays:

 Color displays are extremely popular.

- Some accept information as a composite video signal
(similar to TVs), as TTL voltage level signals (0 or 5V) and as
analog signals (0 to 0.7V).

 Composites are disappearing since high-resolution cannot

be achieved.
- They combine the color information with other
information such as sync pulses.

 Most modern systems use direct video signals with separate

sync signals.
- Monochrome monitors use one wire for video, one for
horizontal sync and one for vertical sync.
- Color monitors use three video signals, one for red,
green and blue (RGB).

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The TTL RGB Monitor:

 It uses TTL level signs (0 or 5V) as video inputs and a 4th line
called intensity.

 It can display a total of 16 different colors (CGA in older systems)

 Cyan is a combination of Green and Blue, Magenta - Red and

Blue, etc.

- Horizontal and vertical retrace are for synchronization.

Normal video is used for 'intensity' on monochrome monitors.

The connector pin definitions for either color or monochrome

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The following table gives the RGB values and colors:

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Analog RGB Monitors

- Analog RGB monitors have 3 video signals (no intensity) that

can be driven with values
between 0 and 0.7 V.

- Most can display 256K, 16M or 24M colors.

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 Most analog displays use a DAC to generate each color video

voltage.

 A common standard uses a 6-bit DAC for each video signal for
64 distinct voltage levels over 0 to 0.7 V range.

- 64 X 64 X 64 = 262,144 (256K) colors.

8-bit DACs yield 16M colors.

 Conversion time between 25ns and 40ns is required of the DAC.

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