By

V.SIDDHARTHA
O3-10-EV013
Introduction Conventional Bi-CMOS Inverter

Characteristics Bi-CMOS Process Flow

Evolution Basic Bi-CMOS Logic Gates

Comparison between CMOS & Bi- Pros and Cons

CMOS
Applications
Basic CMOS Inverter

Basic Bi-CMOS Inverter

In integrated circuit technologies, BiCMOS, also called BiMOS, refers to
the integration of bipolar junction transistors and CMOS technology into
a single integrated circuit device.

Having realized the advantages of the two technologies the designers

have decided to integrate both the technologies into a single chip.
BiCMOS technology enables high performance integrated circuits
ICs but increases process complexity.

Delay and Power

CMOS

DELAY Bi CMOS

ECL

POWER
 1st GENERATION (1969 -mid 1970s):
• 1st publication in 1969 (by H.C. Lin).
• BiCMOS OPAMPs by RCA in the mid 1970s.

 2nd GENERATION (1970s -mid 1980s):

• Smart Power (major product).
• BiDEFT

 3rd GENERATION (mid 1980s -present):

• 5V Digital BiCMOS (major)
• Motivated by
1. Power dissipation constraints of BJT
2. Speed limitations of MOSFET
3. Requirements for higher I/O throughput
 The following schematic explains about Speed comparison
 The following schematic
explains about Delay comparison

 The following schematic

explains about area comparison
 The following schematic explains about basic CMOS Inverter
 The following schematic explains about basic BiCMOS Inverter
 The following schematic explains about convectional BiCMOS Inverter

Vdd  

Vin T2  
T4  
Vout
T6  

T1  
T3  
T5   CL  
• STEP 1: Figure showing Device cross-section of BiCMOS process showing
N+ buried layer implant.  
• STEP 2: Figure showing Device cross-section of BiCMOS process showing P
buried layer self aligned implant.
• STEP 3:Figure showing Device cross-section of BiCMOS process after growth
of the EPI-layer.
• STEP 4:Figure Device cross-section of BiCMOS process showing EPI-layer
masking for N-well implant.
• STEP 5: Figure showing Device cross-section of BiCMOS process showing
self-aligned P-well implant. Previously, the N-wells were implanted and a
350nm oxide is grown, which serves as blocking mask for the P-well
implant.
• STEP 6: Figure showing Device cross-section of BiCMOS process showing
channel stop implant. Before, the wafer was planarized and patterned.
• STEP 7: Figure showing Device cross-section of BiCMOS process showing
deep N+ subcollector implant. The PMOS and NMOS devices are protected
by the photo resist.
• STEP 8:Figure showing Device cross-section of BiCMOS process showing
the intrinsic base implant.
• STEP 9:Figure showing Device cross-section of BiCMOS process showing
the fabrication of the polysilicon emitter. The emitter window is opened,
followed by the polysilicon deposition. The polysilicon is implanted and
will serve as out diffusion source to form the emitter junction.
•STEP 10: Figure showing Device cross-section of BiCMOS process before the
NMOS LDD doping is implanted. The subcollector is opened to collect
additional N-type doping.
• STEP 11:Figure showing Device cross-section of BiCMOS process showing
the source-drain implantation of the NMOS device.
• STEP 12:Figure showing Device cross-section of BiCMOS process showing
the PMOS source-drain implantation, which is also applied to the base to
form the extrinsic base doping.
• STEP 13:Figure showing Device cross-section of BiCMOS process after
fabrication of the active areas. The source-drain anneal is optimized to
emitter out diffusion conditions. Afterwards the structure is scheduled for a
double-level interconnect process.
• Bi-CMOS NAND GATE
• Bi-CMOS NOR GATE
 High impedance CMOS transistors may be used for the input circuitry while the
remaining stages and output drivers are realized using bipolar transistors. 

 Compared to CMOS, BiCMOS reduced dependence on capacitive load and the

multiple circuit and I/Os configurations possible greatly enhance design
flexibility and can lead to reduced cycle time (i.e., faster circuits).

 BiCMOS is inherently robust with respect to temperature and process

variations, resulting in less variability in final electrical parameters, resulting in
higher yield, an important economic consideration.
 
Greater process complexity compared to CMOS.

Results in a 1.25 -> 1.4 times increase in die costs over conventional CMOS.
Taking into account packaging costs, the total manufacturing costs of supplying
a BiCMOS chip ranges from 1.1-> 1.3 times that of CMOS.
 Semi custom ICs

 Register, Flip-flop

 Standard cells

 Full custom ICs

– SRAM,DRAM
– Microproessor,controller
– Adders, Mixers, ADC, DAC

 Gate arrays
 The extra process complexity requires chip manufacturers to command a
premium for BiCMOS products.

 BiCMOS is a complement to pure CMOS and Bipolar technologies in

important system application areas.