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Multipliers
© Multipliers are among the fundamental components of
many digital systems

© The largest contribution to the total power

consumption in the multiplier is due to the generation
of partial product

© Among all the multipliers shift and add multipliers are

the most commonly used ,due to its simplicity &
relatively small area requirement
 Multipliers
© |igher radix multiplier are faster but consumes more
power

© In this work we propose some modifications to the

conventional shift and add architecture
Main Sources of Switching Activity
1. Shifts of the B register,

2. Activity in the counter,

3. Activity in the adder,

4. Switching between '0'

and A in the multiplexer,

5. Activity in the mux-

select controlled by
B(0),and

6. Shifts of the partial

product (ëë) register.
ëroposed Low ëower
Multiplier: BZ-FAD
SHIFT OF B REGISTER:
In the traditional architecture, in
each cycle B is shifted to the right at,
so that its right bit appears at b(0).

If b(0) is 0,then Ǯ0ǯ is added with pp,

else A is added with pp

In the proposed architecture, a

multiplier(M1) with one encoded bus
selector chooses the hot bit of B in
each cycle.

A low power ring counter is used to

select b(n) in nth cycle, which is wider
than the binary counter used in
conventional multiplier
 ëroposed Low ëower
Multiplier: BZ-FAD

Reducing the Switching

Activity of the Adder

§educing the unnecessary activities

of the adder when b(0) is zero

Eliminating the unnecessary

activities using bypass and feeder
register

§emoval of multiplexer.

In this work we use ripple carry

adder,which has least transitions per
addition among all the adders
 Proposed Low Power Multiplier: BZ-FAD
Shift Of PP Register

In conventional multiplier

multiplication is completed only by
processing MSB

Notice that in Fig 2 for ë Low, the

lower half of the partial product, we
use latches (for a k-bit multiplier).

In the 1st cycle LSB ëë(0) of the

procedure becomes finalised &
stored in the right most bit of ëlow
Proposed Low Power Multiplier: BZ-FAD

Shift Of PP Register

 §ing counter o/p is used to

open the latch,using S/| line
for nth latch in nth bit ring
counter

 When the last bit is stored in

the leftmost latch, the higher
and lower halves of the partial
product form the final product
result.
©
 §ing counter
© In a ring counter always a single '1' is
moving from the right to the left.
Therefore in each cycle only two flip-
flops should be clocked. To reduce the
switching activity of the counter, we

© Once the Entrance signal becomes '1', the

sample and datain lines of the latch are
set to '1'.

© The clock pulses come to the clock

gating structure, propagate through
the NAND gate, and go to the block
cells via Clock-OUT, until the Exit
signal becomes '1'.
 §esults and discussion
Ring counter

As seen in this diagram, the

efficiency of the |ot Block
architecture is more pronounced as
the width of the ring counter
increases

The clock gating structure used in

ring counter is implemented using 18
transistor(10+4+4)
As the block size increases the area
overhead decreases. Each ff need 18 transistors and hence for
block size of area over head is given by(2)
|owever, the larger the block size is,
the higher the power consumption is.
 RESULTS & DISCUSSION
Multiplier

To determine the effectiveness of the power reduction techniques discussed

we have reported in Table the switching activities of major common blocks of
the BZFAD and conventional multipliers.
 RESULTS & DISCUSSION
Multiplier
To evaluate the efficiency of the proposed architecture, we implemented three different
Radix-2 16-bit multipliers corresponding to the conventional, BZ-FAD and SëST
architectures.

As another comparison, the power consumption of the multipliers for

normally distributed input data are reported
 RESULTS & DISCUSSION
Multiplier

In Fig 7, the area overhead and the power reduction of the BZ-FAD multiplier are
compared with those of the SPST multiplier.
 RESULTS & DISCUSSION
Multiplier

Comparison between Fig 1 and Fig 2 reveals that M1, M2 and the ring counter
are responsible for additional area in the proposed architecture. The area
overheads of the ring counter and multiplexers M1 and M2 scale up linearly
with the input data width.
 Summery and conclusion

‰In this paper, a low-power architecture for shift-and-add multipliers was

proposed.

‰ The modifications to the conventional architecture to reduce power

consumption was introduced.

‰The results showed an average power reduction of 30% by the proposed

architecture.

‰We also compared BZ-FAD results with conventional and other

multipliers
 Summary and conclusion

‰The comparison showed that the power saving of BZ-FAD was only 6% lower
than that of SPST whereas the SPST area was five times higher than that of the
BZ-FAD.

‰Thus, for applications where small area and high speed are important
concerns, BZ-FAD is an excellent choice.

‰The simulation results showed that in comparison with the conventional

architecture, the proposed architecture reduced the power consumption more
than 75% for the 64-bit counter.
Any Questions?

Any Questions?
r ANK YOU
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