Thermal Simulation Techniques

for Nano Transistors

Ken Goodson

Mechanical Engineering Department

Stanford University
 Micro Heat Transfer Lab
Ken Goodson, Stanford Mechanical Engineering
Stanford
Roger Flynn Milnes David Dr. Carlos Hidrovo
Xuejiao Hu Julie Steinbrenner Dr. Ching-Hsiang Cheng
Sungjun Im (Materials Science) Evelyn Wang Dr. Eric Pop
Kevin Ness Ankur Jain Dr. Sanjiv Sinha
Jae-Mo Koo John Reifenberg
Yue Liang Eon Soo Lee
Angela McConnell Jeremy Rowlette (Electrical Engineering)
Matt Panzer Fu-Min Wang
David Fogg Caitlin Quance

Alumni
Prof. Mehdi Asheghi Carnegie Mellon University (ME)
Prof. Dan Fletcher UC Berkeley (Bioengineering)
Prof. Bill King Georgia Tech (ME)
Prof. Katsuo Kurabayashi University of Michigan (ME)
Prof. Sungtaek Ju UCLA (ME)
Prof. Kaustav Banerjee UC Santa Barbara (EE)
Dr. Uma Srinivasan Xerox
Dr. Per Sverdrup Intel
Dr. Peng Zhou Cooligy
Dr. Maxat Touzelbaev AMD
Dr. Sanjiv Sinha Intel
 Challenging (and Exciting) Time
for IC Thermal Management
Thermal issues are in the headlines:
Pumped liquid cooling in laptops and
desktops (Hitachi/Toshiba/Apple).
Motivation for multi-core processors.

0.3 oC/W
Rtotal (ITRS 2003)

0.2
Rheat sink

3DIC
Unprecedented startup
0.1 climate for thermal
technologies, ranging
Multicore
Rchip from microfluidics to
0 interfaces (>$100
2000 2005 2010 2015 2020 Million VC per year).
Thermal Resistance Hierarchy
Cinterconnect Device-Level SEM
Tinterconnect
qinterconnects metal
~ 10 ns ILD
Rinterconnect
Ctransistor
qtransistors
Ttransistors
~ 100 ps
Cchip
Rtransistor IBM

Tjunction
chip

~ 100 s
Rchip + TIM chip carrier
C heat sink
Tspreader Si chip
heat spreader
~1s Rheat sink heat sink

Tambient
Outline
1. On-Chip Thermal
Challenges

2. Phonons and Electrons

3. Nano Transistor
Simulations
 On-Chip Thermal Challenges
40
Global Wires With Vias
Interconnect Tech. Node
22 nm
Temperature 30
32 nm
Field 45 nm
20 65 nm

T [ C]
90 nm

o
Student: Sungjun Im,
Trans Electron 10
Devices, in press 2005.

0
Silicon 0.0 0.2 0.4 0.6 0.8 1.0
Normalized Distance from Substrate

Interconnect
self heating
Rinterconnect

1995 2000 2005 2010 2015

 On-Chip Thermal Challenges
Frame 001  01 Jul 2002 

150

140
0.3 oC/W
50 W 130

120
Rtotal (ITRS 2003)
110

100

0.2

Rheat sink
90

80

100 W 70

60
3DIC
50

40

30
0.1
20

10
Multicore
0
Rchip
0
2000 2005 2010 2015 2020
Microprocessor hotspots &
power density (mm scale)
Rchip + TIM

Interconnects

1995 2000 2005 2010 2015

 On-Chip Thermal Challenges
100 0.4
18 nm
Power
-
Density
W/m3
50 On-State 0.2
Power
mW

0 0
2004 2006 2008 2010 2012 2014 2016 2018
Transistor hotspots, leakage,
mobility reduction
Rtransistor

Microprocessor hotspots

Interconnects

1995 2000 2005 2010 2015

 Transistor Evolution
Oxide Silicide
Isolation Gate

Source Drain

Bulk Silicon

Bulk FET

1
Channel Length (nm)
350 130 45 18 10

1995 2000 2005 2010 2015

1
ITRS 2003
 Transistor Evolution
Oxide Silicide
Isolation Gate

Source Drain
FinFET

Bulk Silicon

Bulk FET UC Berkeley/AMD

Carbon nanotube
transistor
Strained Si, Ge, SiGe HfO2
Silicide top gate (Al) CNT
SOI/SiGe Gate
S (Pd) D (Pd)
SiO2
Buried oxide
back gate
Silicon substrate (p++ Si)

IBM Stanford

1995 2000 2005 2010 2015

Outline
1. On-Chip Thermal
Challenges

2. Phonons and Electrons

3. Nano Transistor
Simulations
 Phonon Overview
Responsible for heat conduction in semiconductors optical

Coupled motions of atoms obeying Newton

F = ma

Particles with discrete momentum & energy

p = hq
acoustic
E = h

Described using wavevector and branch

in a dispersion relationship Silicon [100]

Optical Acoustic
(slow) (fast)
 Electrothermal Processes

High Electric
Field

Hot Electrons
225 nm (Energy E) E > 60 meV
 ~ 0.1ps
IBM E < 60 meV
 ~ 0.1ps Optical
OpticalPhonons
Phonons

lattice wave
 ~ 10ps
 electron Acoustic
AcousticPhonons
Phonons
high
electron  ~ 1 ms–1s
 energy d
defect
phonon
E   Heat Transfer
to Package
dopant
phonon
atom

Material boundary with roughness 

Methods to Calculate Heat Generation
Oxide

Lumped Element: q  IV Gate

Drain
Drain
Simple Drift-Diffusion q ' ' '  j E
10 nm

Comprehensive Drift-Diffusion (e.g., Wachutka, 1993)

 j 2 j
2

q' ' '   n

p

 en n ep p 
 
   rr  rg  E Fn  EFp  eT  Pp  Pn   T  jn  Pn  jp  Pp 
 

Hydrodynamic with Separate Electron & Phonon Temperatures

(Shur, 1990; Lai et al., 1995)
 3   3 
Wn  nk B Ts  W p  pk B Ts 
q' ' '  
2  2   r  Wn  W p  E 
r g 
 ns,E  ps,E  n p 

Electron Monte Carlo (Jacoboni, 1983; Fischetti, 1988; Pop et al., 2005)

  gen  abs 
1 d
q' ' ' 
t dV
Monte Carlo Simulation of Heat Generation
(Pop, Sinha, Goodson, Proc. IMECE 2002, Submitted to Journal of Applied Physics)

 2  k x2 k y k z2 
2
• Electrons treated as semi-classical
particles E 1   E    
2  mx m y mz 

• Electrons drift (free flight), scatter
2
M ( k ) g  E k   q 
and select new state 2
(k ) 
• Yields full information about phonon 
generation (Jacoboni, 1983)

optical
intervalley
g
f
intravalley
f
g

acoustic

k  k  q  G
 Monte Carlo of 1D Diode
Thesis work of Eric Pop

N+ N+
i-Si

qV
 Impact of Ballistic Transport
Potential (V)
L=500 nm 100 nm 20 nm
Monte Carlo

Drift-Diffusion

Heat Gen. (eV/cm3/s)

Monte Carlo
Monte Carlo
Drift-diffusion L Drift-diffusion

Error: L/L = 0.10 L/L = 0.38 L/L = 0.80

• MONET vs. Medici (drift-diffusion commercial code):

– “Long” (500 nm) device: same current, potential, nearly identical
– Importance of non-local transport in short devices
– MONET  heat dissipation inside DRAIN (optical, acoustic) of shortest devices
 Phonon Simulation Hierarchy
Continuum  
~ 300 nm at 300 K in Si Fourier’s Law, FEA q "   k T
d~
lattice wave


Phonons
nq  n  nq
defect d  vq .nq   q
phonon BTE & Monte Carlo t q
E  

d~

Waves & Atoms

Waves & Atoms
MDS & QMDS
Thermal Conductivity (W m-1K-1) Silicon Film Conductivities
McConnell, Srinivasan, and Goodson, JMEMS 10, 360-369 (2001)
4
10 Bulk single-crystal silicon:
bulk Touloukian et al. (1970)
d = 0.44 cm
single
1000 crystal Undoped single-crystal film:
films Asheghi et al. (1998)
size d = 3 m
effect Doped single-crystal film:
100
Asheghi et al. (1999)
undoped d = 3 m
doped n = 1·1019 cm-3 boron
10 Doped polysilicon film:
doped undoped poly- McConnell et al. (2001)
crystal d = 1 m
1 dg = 350 nm
10 100 n = 1.6·1019 cm-3 boron
Temperature (K) Undoped polysilicon film:
1 Srinivasan et al. (2001)
1 A 
k (d G , n)  Cv 1  A2 ni  d = 1 m
3  dG  dg = 200 nm
Outline
1. On-Chip Thermal
Challenges

2. Phonons and Electrons

3. Nano Transistor
Simulations
 Transistor Simulation Regime Map
Atomistic

Fundamental
BTE with
Research
Phonons

,
Wave models , Ju 0 0)
p 0
d r u n (2
er so
S v od r
Go da
BTE or m
M aj u
Monte Carlo i,
rk La 995)
wo a (1 )
h k
uc hut 9 9 0 5)
1 9
m ac )
u r ( ( 19
W 994 S h vi ch
Diffusion (1 o 0)
p an 1 97 ) )
83 ) 3)
2) A e r ( 985 9
(1 88 20
0 m
96 j a (1 ni (19
( tro 95)
(1 ek ani 6) o ad s
n oe r
t b ti st
e nd ( 1 9
tto Bl cca (19
8
a co het in u
L tta
ra J i sc W Da
St Ba dan F
Isothermal Ru
Drift Diffusion

Monte Carlo

Models
with Quantum
Moments

Monte Carlo
BTE

& BTE

Full Quantum
Electrons
 Transistor Simulation Regime Map
Atomistic
Transistor Requirements
Available electrons phonons
BTE with
Software
Phonons

Wave models
~5 nm ~100 nm
MFP
BTE or
Monte Carlo  ~5 nm ~1 nm

Diffusion

Currently
??
Available
Isothermal
Drift Diffusion

Monte Carlo

Models
with Quantum
Moments

Monte Carlo
BTE

& BTE

Full Quantum
Electrons
 Monte Carlo of 18 nm Thin-Body
SOI Transistor
ITRS Specs:
Current

LG=18 nm, tSI=4.5 nm, tOX=1 nm

NSD=1e20 cm-3, NCH=1e15 cm-3
ION=1000 A/m, IOFF=1 A/m
GATE=4.53 eV (Mo), VDD=0.8 V
if W/L = 4 then Nelec ~ 2500 total!
J·E

Eric Pop, 2004

 Transistor Simulation Regime Map
Atomistic
atomistic hotspot relaxation
calculations Stanford
BTE with
Research
Phonons

Atomistic
models split flux phonon BTE http://nanoheat.stanford.edu
BTE or
Electron MONET
Monte Carlo Monte
Carlo
with
ESD phonon
Diffusion
Studies dispersion
& branch
accuracy
Isothermal
Drift Diffusion

Monte Carlo

Models
with Quantum
Moments

Monte Carlo
BTE

& BTE

Full Quantum
Electrons
 Monte Carlo Implementation: MONET
E. Pop et al., J. Appl. Phys. 2004
optical
2 k2
k 2
k 
2
E 1   E  
  y
x
  z
2 m m mz  50 meV
 x y

Phonon Freq.  (rad/s)

Typical
MC codes
Density of States (cm-3eV-1)

Analytic band

q  0  vs q  cq 2
Full band
OK to use 20 meV
acoustic

Energy E (eV) Wave vector qa/2

• Analytic (non-parabolic) energy bands, quadratic phonon dispersion

• First analytic-band code to distinguish between all phonon modes
• Easy to extend to other materials, strain, confinement
 Monte Carlo of 18 nm Thin-Body
SOI Transistor
ITRS Specs:
Current

LG=18 nm, tSI=4.5 nm, tOX=1 nm

NSD=1e20 cm-3, NCH=1e15 cm-3
ION=1000 A/m, IOFF=1 A/m
GATE=4.53 eV (Mo), VDD=0.8 V
if W/L = 4 then Nelec ~ 2500 total!
J·E

Eric Pop, 2004

Phonon Transients during Switching

Sanjiv Sinha
 Hotspot Temperature

ULTRA-THINBODY
Temperature (oC)

Actual Junction
Temperature

Hotspot Targeted Junction

Effect Temperature

Year1 1
Based on ITRS 2003
 Molecular-Dynamics Simulations of Phonons†
0.8
Sinha et al., J. Appl. Phys., 97, 23702 (2005)
0.6 LO phonon wave packet
0.4
(longitudinal displacements)

0.2

uz/a0 x 103
0

-0.2

-0.4

-0.6

-0.8
0 200 400 600 800 1000
z (nm)
1 m 0.35

0.3 LO phonon wave packet

• Stillinger-Weber Potential for Si 0.25
(energy)

• 64,000 atom system

E - E0 (meV)

0.2

• 2x2x2000 unit cells 0.15

• Simulation time ~ 5 days on 48
0.1
Pentium class nodes for 0.5 ns
data 0.05

†
In collaboration with Drs. Phillpot & 0
0 200 400 600 800 1000
Schelling at Argonne National Lab z (nm)
 Atomistic Simulation of Phonon
Hotspot Decay
Sinha, Schelling, Phillpot, and Goodson, Journal of Applied Physics 2005

Low amplitude LO High amplitude LO

• Anharmonic phonon-phonon interactions promote scattering at

higher hotspot energy densities
• Decay of optical phonon creates slow traveling zone-edge
acoustic phonons, reducing heat conduction after scattering
 Concluding Remarks
• The semiconductor research community is pursuing
transistor (FinFET, SOI, SiGe, thin oxide) and circuit
geometries (3D-IC) that will dramatically amplify on-chip
temperature differences.

• Within the next several years, “nano” transistors will

produce hotspot temperature differences comparable with
those in the package and case. These hotspots will be
important both for leakage and drive currents in future
technologies.

• There is an important need for experimental results for nano

transistors, in particular for transient electron and phonon
populations during switching.
 Micro Heat Transfer Lab
Ken Goodson, Stanford Mechanical Engineering
Stanford
Roger Flynn Milnes David Dr. Carlos Hidrovo
Xuejiao Hu Julie Steinbrenner Dr. Ching-Hsiang Cheng
Sungjun Im (Materials Science) Evelyn Wang Dr. Eric Pop
Kevin Ness Ankur Jain Dr. Sanjiv Sinha
Jae-Mo Koo John Reifenberg
Yue Liang Eon Soo Lee
Angela McConnell Jeremy Rowlette (Electrical Engineering)
Matt Panzer Fu-Min Wang
David Fogg Caitlin Quance

Alumni
Prof. Mehdi Asheghi Carnegie Mellon University (ME)
Prof. Dan Fletcher UC Berkeley (Bioengineering)
Prof. Bill King Georgia Tech (ME)
Prof. Katsuo Kurabayashi University of Michigan (ME)
Prof. Sungtaek Ju UCLA (ME)
Prof. Kaustav Banerjee UC Santa Barbara (EE)
Dr. Uma Srinivasan Xerox
Dr. Per Sverdrup Intel
Dr. Peng Zhou Cooligy
Dr. Maxat Touzelbaev AMD
Dr. Sanjiv Sinha Intel
EXTRA SLIDES
CMOS Transistor Technologies
Strained-Si
channel Tbody
Gate Gate Gate

Source Drain Source Drain Source Drain

Relaxed SiGe
SiO2
Graded SiGe
Lch Si substrate Si substrate

Bulk FET Strained-Si FET Thin Body SOI

• Bulk FET “workhorse” of semiconductor industry,

Lch = 130 nm today  10 nm in 2016 (?)
• Strained-Si channel offers mobility improvement
• UTB-SOI reduces short channel effects and
substrate capacitive coupling
 Nanotransistor Geometries

Gate
Tbody Drain
Gate
Source Drain

Gate
Source

Double-Gate SOI FinFET

(Purdue, IBM) (UC Berkeley, AMD, IBM)

PillarFET
(UT Austin)

• DG-SOI reduces vertical field, enhances control of short

channel, hard to fabricate buried gate
• FinFET thin vertical structure, dual gate
• PillarFET integrates material and geometry benefits
 Electrothermal Simulation Strategy

E
Hot Electrons Monte-Carlo

Hot Phonons Phonon BTE

Split-Flux Model
Thermal Phonons Heat Diffusion

Heat Sink nk, s nk, s

 v  nk, s    n k, s
t  k ,s


T E NE 
 
 
C   Q   J NE  KT
t t

90 nm bulk

Sanjiv Sinha
 Fully-Coupled Simulations – Monte Carlo

ITRS 20nm (2009) node Rsource,drain < 840 Ohm/Sq.

Effect of Source/drain
resistance is amplified: Uncoupled

Voltage [V]
Coupled

Position [nm]
 A Multiscale, Multi-Carrier Approach
Sponsorship: IBM, SRC, and Intel. Students: Eric Pop, Sanjiv Sinha

MONET

nq  nq  nq
 vq .nq  
t q
fast Monte Carlo for electron and
phonon distributions in nanodevices

• Electron Monte Carlo (MONET, see http://nanoheat.stanford.edu)

– Calculate spatial and k-space distribution of electrons & generated phonons
– Determine impact of non-thermal phonon populations on device resistance
• Atomistic Simulations (with S. Phillpot, P. Schelling, Argonne National Lab, U. Florida, U. C.
Florida)
– Calculation of relaxation times for phonons
– Study of phonon interface / wave effects in nanotransistor geometries
• Phonon BTE / Monte Carlo
– Determine transport of optical and acoustic phonons in realistic device geometries
– Provide phonon populations for electron Monte Carlo
• Diffusion Equation
– Conduction to the bulk of the substrate and to material boundaries
– Thermal interactions among devices on a given substrate
Fully-Coupled Simulations - Hydrodynamic
Chun, Kim, Liu, Tornblad, Dutton. Proc SISPAD 2005

To To  Ta Co ( Ca ) : optical (acoustic) phonon

Co  H    (oTo)  Co
t o heat capacity
Ta To  Ta To ( Ta ) : optical (acoustic) phonon
Ca    (aTa )  Co temperature
t o
: energy relaxation time between
3 Tc  To optical and acoustic phonon
H  n  kB 
2  o

Gate Gate
450 430 390 410

Source Drain Si Source Drain Si

360 370 SiO2 SiO2
350 360
350 340
Lch Lch

Optical phonon temperature Acoustic phonon temperature

 On-Chip Thermal Challenges
Advanced technologies (shallower
junctions, thinner oxides, SOI/SiGe,
novel geometries) all aggravate
ESD failures

6
5 CDM
4

IESD (A)
3
2 HBM
1
Metal/via damage
K. Banerjee et al., IRPS 1996 -1
MM
0 20 40 60 80 100 120ns

Electrostatic Discharge

1995 2000 2005 2010 2015

 Timescales of Transistor
Electrothermal Processes
6
5 CDM
Governs total power
4
consumption, package-
IESD (A)

3
level cooling
2 HBM Governs peak transistor
1
temperature & mobility
Governs relative
-1 reduction, leakage
MM importance of
augmentation
0 20 40 60 80 100 120ns failure modes for ESD

gate
Stress switching ESD / EOS Phenomena
Timescales clock
period

conduction processes within

Mechanistic transistor and gate oxide
diffusion processes within
Timescales electron & phonon interconnects, vias, passivation
relaxation times

10-12 10-11 10-10 10-9 10-8 10-7

seconds