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a Logicalartitionsofisk

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a ntroductiontontelicroprocessor
a ntelrchitecture

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Key Features:
a Released by Intel in 1978
a Produced from 1978 to 1990s
a A 16-bit microprocessor chip.
a Max. CPU clock rate :
5 MHz to 10 MHz
a Instruction set: x86-16
a Package: 40 pin DIP
a The 8086 gave rise to Fig1:Intel 8086 Microprocessor
the x86 architecture of Intel's future processors.
a Common manufacturer(s): Intel, AMD, NEC, Fujitsu, Harris
(Intersil), OKI, Siemens AG, Texas Instruments, Mitsubishi.
The Intel 8088, released in 1979, was a slightly modified
chip with an external 8-bit data bus and is notable as the
processor used in the original IBM PC.

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a he architecture was defined by „

  


with soe help and assistance by  



(the architect of the  in refining the final
revisions. Logic designer   
 and 


were the lead engineers of the hardwarelevel

developent tea and   the
anager for the project.
a he legacy of the  is enduring in the basic
instruction set of today's personal coputers and
servers; the  also lent its last two digits to later
extended versions of the design, such as the ntel
 and the ntel , all of which eventually becae
known as the x faily.
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in

a t was ipleented using depletionload n
circuitry with approxiately , active transistors
( , counting all  and L sites.
a t was soon oved to a new refined n
anufacturing process called H (for High
perforance  that ntel originally developed for
anufacturing of fast static  products.
a his was followed by H, H versions,
and, eventually, a fully static  version for
batterypowered devices, anufactured using ntel's
H processes.
a he original chip easured  (assue a
square of side length=.c and iniu feature
size was . .
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a here is need to study a icroprocessor. How it works, what is its
architecture, what is its instruction set architecture, how it is
prograed, how it is interfaced with other devices etc. etc.
a  is first x icroprocessor.
he ter x86 refers to a faily of instruction set architectures based
on the ntel  . he  was launched in |  as a fully |
bit extension of ntel's early bit based icroprocessors and also
introduced segentation to overcoe the |bit addressing barrier of
earlier chips. he ter x derived fro the fact that early successors
to the  also had naes ending in "". any additions and
extensions have been added to the x instruction set over the years,
alost consistently with full backward copatibility.he architecture
has been ipleented in processors fro ntel, yrix, , V, and
any others.
a he  arket which uses ntel based devices takes up soe  of
the total icroprocessor arket! he other ain processor used by
industry is the otorola  faily of icroprocessors.
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Key features of this trainer kit are such as:
a 
  operating at .
 Hz.
a | %&  with &attery backup expandable upto 
%&.
a | %& powerful onitor  .
a  
 lines using .
a | bit ier
ounter using  .
a   nterface using |.
a  nterrupt ontroller.
a  eries   rograer.
a rinter nterface [ptional].

These kits are prepared and supplied by

many suppliers in India also for training and
education purpose.
Fig: 8086 kit
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.
System Overview
The 8086 is probably the most commonly used 16-
bit microprocessor of all time, with the upwardly
compatible families of microprocessors developed
from it now at the heart of the virtually all personal
computers. This makes the 8086 the number one
choice as a platform for teaching microprocessor
principles on many computer science courses.

Fig2
Fig1: 8086 kit

The FLT86 is a well established training system for the 8086 CPU still being
manufactured by Flite Electronics International Limited in Southampton, England.
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Address Bus ± 20 lines ± A19 ± A0
Add
Bus

Data Bus ± 16 lines ± D15 ± D0

Data
icroprocessor Bus


a |bit icroprocessor' Control

a |bitsdatabus' signals

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a It can address any one of | (((((
1,048,576 (=220
) memory ((((((. H
locations/addresses.
a Each memory location is
one byte wide. |((((((.| H
a To store a word of 16 bit H
2 memory locations are
required.
a If the first byte of the
word is at even address
8086 can read the entire
word in one operation. eory
a If the first byte of the ddress
word is at an odd
address, the 8086 will pace
read the first byte with
one bus operation and
the second byte with
another bus operation.
1,048,576 memory locations=1MBytes H
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 INiNA! AIii

2 units are:
1. BIU
2. EU

Fig: 8086 Internal block diagram .

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a BIU (bus interface unit) sends out
addresses, fetches instructions fro eory,
reads data fro ports and eory, and
writes data to ports and eory. n other
words, the & handles all transfers of data
and addresses on the buses for the execution
unit.
a EU (execution unit) of the  tells the &
where to fetch instructions or data fro,
decodes instructions, and executes
instructions.
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