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 What was SPI (Serial Peripheral
Interface)Bus?
‡ SPI specifies four signals:
± clock (SCLK): Clock, is generated by the master and input to all slaves.
± master data output, slave data input (MOSI); carries data from master to slave.
± master data input, slave data output (MISO); carries data from slave back to master.
± slave select (ÇSS): Chip select-bar, A slave device is selected when the master asserts its ÇSS signal.
‡ Each device has a separate chip-select signal, so that the µP can address the
appropriate part by the relevant CS-bar signal.
‡ The SPI-bus is well suited to data-rates to 20Mbps. Some devices (e.g., RTCs like
the MAX6901) have a 3-wire interface, where the data-line is bi-directional. This
interface is similar to SPI.
‡ There is a MASTER and a SLAVE mode. The MASTER device provides the clock
signal and determines the state of the chip select lines, i.e. it activates the SLAVE it
wants to communicate with. CS and SCKL are therefore outputs. The SLAVE device
receives the clock and chip select from the MASTER, CS and SCKL are therefore
inputs. This means there is one master, while the number of slaves is only limited
by the number of chip selects.
‡ The SPI requires two control lines (CS and SCLK) and two data lines (SDI and SDO).
Motorola names these lines MOSI (Master-Out-Slave-In) and MISO (Master-In-
Slave-Out). The chip select line is named SS (Slave-Select).
‡ Because there is no official specification, what exactly SPI is and what not, it is
necessary to consult the data sheets of the components one wants to use.
‡ SPI can also achieve significantly higher data rates than I2C.
 What was SPI (Serial Peripheral
Interface)Bus?

‡ SPI-compatible interfaces often range into the tens of megahertz.

‡ SPI devices communicate using a master-slave relationship.
‡ Both SPI and I2C offer good support for communication with low-speed devices, but
SPI is better suited to applications in which devices transfer data streams.
|
 

 |
 
 What was I2C [standard Inter-IC (integrated circuit)] Bus?

‡ The I2C-bus has 2 signals:

± SCL = Serial Clock
± SDA = Serial Data in/out.
‡ Each device has a unique 7-bit or 10-bit address.
‡ The data-line is bi-directional, only 2 wires are required.
‡ Standard I2C devices operate up to 100Kbps, while fast-mode devices operate at up to
400Kbps. A 1998 revision of the I2C specification (v. 2.0) added a high-speed mode running at
up to 3.4Mbps. .Most available I2C devices operate at speeds up to 400Kbps.
‡ Most often, the I2C master is the CPU or microcontroller in the system.
‡ Each device must have a unique 7-bit I2C address so that the master knows specifically who it
is communicating with. Typically the first four bits are fixed and assigned to specific categories
of devices, e.g. 1010 is assigned to serial EEPROMs. The next three bits (e.g.,A2,A1 and A0)
are set by hardware address pins on the package that modify the I2C address allowing up to
eight different address combinations and therefore allowing up to eight identical devices to
operate on the I2C bus.
‡ The last bit of the initial byte indicates if the master is going to send (write) or receive (read)
data from the receiver, typically a slave device. Each transmission sequence must begin with
the start condition and end with the stop or restart condition. If there are two masters on the
same bus, there are arbitration procedures if both try to take control of the bus at the same
time. Once a master (e.g., microcontroller) has control, no other master can take control until
the first master sends a stop condition and places the bus in an idle state.
 I2C Communication

‡ The master begins the communication by issuing the start condition (S). The
master continues by sending a unique 7-bit slave device address, with the most
significant bit (MSB) first. The eighth bit after the start, read/not-write (),
specifies whether the slave is now to receive (0) or to transmit (1). This is
followed by an ACK bit issued by the receiver, acknowledging receipt of the
previous byte. Then the transmitter (slave or master, as indicated by the bit)
transmits a byte of data starting with the MSB. At the end of the byte, the
receiver (whether master or slave) issues a new ACK bit. This 9-bit pattern is
repeated if more bytes need to be transmitted.
‡ In a write transaction (slave receiving), when the master is done transmitting all
of the data bytes it wants to send, it monitors the last ACK and then issues the
stop condition (P). In a read transaction (slave transmitting), the master does
not acknowledge the final byte it receives. This tells the slave that its
transmission is done. The master then issues the stop condition.
|
 

   
Terminology for  bus transfer

‡ Terminology for  bus transfer:

± F (FREE)²the bus is free or idle; the data line SDA and the SCL clock are both in the
high state.
± S (START) or SR (Repeated START)²data transfer begins with a start condition. The
level of the SDA data line changes from high to low, while the SCL clock line remains
high. When this occurs, the bus becomes busy¶.
± C (CHANGE)²while the SCL clock line is low, the data bit to be transferred can be
applied to the SDA data line by a transmitter. During this time, SDA may change its
state as long as the SCL line remains low.
± D (DATA)²a high or low bit of information on the SDA data line is valid during the high
level of the SCL clock line. This level must be kept stable during the entire time that the
clock remains high, to avoid misinterpretation as a Start or Stop condition.
± P (STOP)²data transfer is terminated by a stop condition. This occurs when the level on
the SDA data line passes from the low state to the high state, while the SCL clock line
remains high. When the data transfer has been terminated, the bus becomes free once
again.
 What was I2S(inter-IC sound) Bus?
‡ A serial link especially for digital audio. A 3-line serial bus is used consisting of a line for two time-multiplexed
data channels, a word select line and a clock line.The bus has three lines:
± continuous serial clock (SCK);
± word select (WS);
± serial data (SD);
the device generating SCK and WS is the master.
‡ Since the transmitter and receiver have the same clock signal for data transmission, the transmitter as the
master, has to generate the bit clock, word-select signal and data.
 What was I2S(inter-IC sound) Bus?
‡ The I2S bus is a three-wire connection that exclusively handles two time-multiplexed data channels.
‡ |
 is transmitted in two¶s complement with the MSB first(because the transmitter and receiver may
have different word lengths).
‡ The MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter
always sends the MSB of the next word one clock period after the WS changes.
‡ The 

  line indicates the channel being transmitted:
± WS = 0; channel 1 (left);
± WS = 1; channel 2 (right).
‡ WS may change either on a trailing or leading edge of the serial clock, but it doesn¶t need to be symmetrical.
‡ The WS line changes one clock period before the MSB is transmitted. This allows the slave transmitter to
derive synchronous timing of the serial data that will be set up for transmission.
‡ TIMING -- In the I2S format, any device can act as the system master by providing the necessary clock
signals.
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 The McBSP is set to dual-phase frame mode by setting the
appropriate bits (R/XPHASE) in the receive/transmit control registers (R/XCR). One phase is for left-channel
data, and the other is for right-channel data. The data word length is set to the appropriate value for both
phases (R/XWDLEN1/2 in R/XCR). The number of words in each phase of the frame is set to 1 R/XFRLEN1/2
in R/XCR = 0). New data words begin one SCK cycle after a change in the WS line (R/XDATDLY in R/XCR =
1).
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#|7<7$ The frame sync signal is configured by setting the
frame width field (FWID), the frame period field (FPER), and the frame synchronization bit (FSGM) in the
sample rate generator register (SRGR). The FSGM bit forces the frame sync to be generated based on the
serial clock regardless of the availability of data in DXR. In this mode, a new frame sync is generated every
FPER + 1 serial clock cycles, and the signal is held active (either indicating a left or right channel word
depending on the polarity bit) for FWID + 1 serial clock cycles. In this way, it is possible to create waveforms
with various periods and duty cycles on the FSX pin.
‡ For I2S, the frame period must be twice the word length, and the frame width must be the word
length.Therefore, FPER in SRGR should be set to (2 * word length ± 1), and FWID in SRGR should be set to
(word length ± 1). This allows the FSX pin to be the WS line for transmission/reception of left and right
channel data, as the WS line is held low for one word length, then high for one word length.
‡ CLKS can be generated from an external oscillator that runs at a multiple of the sampling frequency. For
example, if 48KHz sampling is desired and the left and right channels contain a single 32-bit word, CLKS can
be driven by a 3.072MHz (32 x 2 x 48KHz) oscillator. The sample rate generator clock divider (CLKGDV) field
of SRGR must be chosen such that (CPU clock frequency) / (2 * word length * (CLKGDV + 1)) is less than or
equal to the I2S device¶s maximum sampling/output frequency.
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‡ Set up a DMA channel to service the serial port and sort the data.The following formulas compute the element
and frame index:
± B = Buffer size (total number of elements in each buffer)
± S = Element size in bytes
‡ ELEMENT INDEX = B x S
‡ FRAME INDEX = S ± (B x S)
± Eg :
Figure shows how DMA sorting works. In Figure , the element size S = 4 bytes, and the buffer size B = 0x400 elements in each buffer. The
element index is B x S = 400h x 4 = 1000h. The frame index is S ± (B x S) = -FFC.
‡ To enable DMA auto initialization:
± write START=11b in the channel¶s primary control register,
± and set the corresponding DMA global count reload register
± and the DMA global address register to the desired reload values.

‡If you want to modify the reload register values before the next DMA auto initialization, set TCINT=1 in the
channel¶s primary control register and LAST IE=1 in the channels¶ secondary control register to enable last frame
condition interrupt. the interrupt service routine can modify the reload register values before the next auto
initialization.
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This C code shows how to set up the McBSP and DMA to interface to an I2S device,
The mcbsp.c file sets up the serial ports and DMA channel, and dma_int.c provides the necessary interrupt
service routines.
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