CSE/EE 462: VLSI

Design
Fall 2004
Adders

Jay Brockman

[Adapted from Mary Jane Irwin and Vijay Narananan, CSE Penn State
and Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

CSE/EE 462 L14 Adders.1 Brockman, ND, 2004

 Full-Adder

A B

Cin Full Cout

adder

Sum

CSE/EE 462 L14 Adders.2 Brockman, ND, 2004

 The Binary Adder

A B

Cin Full Cout

adder

Sum

S = A  B  Ci

= ABC i + ABC i + ABCi + ABCi

C o = AB + BCi + ACi

CSE/EE 462 L14 Adders.3 Brockman, ND, 2004

 Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB
Propagate (P) = A  B
Delete = A B

Can also derive expressions for S and C o based on D and P

Note that we will be sometimes using an alternate definition for
Propagate (P) = A  B
CSE/EE 462 L14 Adders.4 Brockman, ND, 2004
 The Ripple-Carry Adder

A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 Co,2

FA FA FA FA
( Ci,1)

S0 S1 S2 S3

Worst case delay linear with the number of bits

td = O(N)

tadder = (N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit

CSE/EE 462 L14 Adders.5 Brockman, ND, 2004

 Complimentary Static CMOS Full Adder

VDD

VDD
Ci A B

A B
A

B
Ci B
VDD
A
X
Ci

Ci A
Ci

A B B VDD
A B Ci A

Co B

28 Transistors
CSE/EE 462 L14 Adders.6 Brockman, ND, 2004
 Inversion Property

A B A B

Ci FA Co Ci FA Co

S S

S  A B C i  = S  A B  Ci 

C o  A B C i  = Co  A B  Ci 

CSE/EE 462 L14 Adders.7 Brockman, ND, 2004

 Minimize Critical Path by Reducing Inverting Stages

Even cell Odd cell

A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 C Co,3

FA FA FA FA

S0 S1 S2 S3

Exploit Inversion Property

CSE/EE 462 L14 Adders.8 Brockman, ND, 2004

 A Better Structure: The Mirror Adder

VDD

VDD VDD A

A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A

24 transistors

CSE/EE 462 L14 Adders.9 Brockman, ND, 2004

 Mirror Adder

Stick Diagram
VDD

A B Ci B A Ci Co Ci A B

Co

GND
CSE/EE 462 L14 Adders.10 Brockman, ND, 2004
 The Mirror Adder

• The NMOS and PMOS chains are completely symmetrical.

A maximum of two series transistors can be observed in the carry-
generation circuitry.
• When laying out the cell, the most critical issue is the minimization of the
capacitance at node Co. The reduction of the diffusion capacitances is
particularly important.
• The capacitance at node Co is composed of four diffusion capacitances,
two internal gate capacitances, and six gate capacitances in the
connecting adder cell .
• The transistors connected to Ci are placed closest to the output.
• Only the transistors in the carry stage have to be optimized for optimal
speed. All transistors in the sum stage can be minimal size.

CSE/EE 462 L14 Adders.11 Brockman, ND, 2004

 Transmission Gate Full Adder

P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

CSE/EE 462 L14 Adders.12 Brockman, ND, 2004

 Manchester Carry Chain

VDD
Pi
VDD 
Pi
Ci Co
Gi
Co Gi
Ci

Di
Pi 

CSE/EE 462 L14 Adders.13 Brockman, ND, 2004

 Manchester Carry Chain

pseudo-NMOS load

P0 P1 P2 P3 P4

Ci,0
G0 G1 G2 G3 G4

CSE/EE 462 L14 Adders.14 Brockman, ND, 2004

 Manchester Carry Chain

VDD

P0 P1 P2 P3
C3

Ci,0
G0 G1 G2 G3

C0 C1 C2 C3

CSE/EE 462 L14 Adders.15 Brockman, ND, 2004

 Manchester Carry Chain

Stick Diagram
Propagate/Generate Row

VDD
Pi Gi  Pi + 1 Gi + 1 

Ci - 1 Ci Ci + 1

GND

Inverter/Sum Row

CSE/EE 462 L14 Adders.16 Brockman, ND, 2004

 Carry-Bypass Adder

P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci,0 C o,0 C o,1 Co,2 Co,3
FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA

Multiplexer
Co,3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C 0, else “kill” or “generate”.

CSE/EE 462 L14 Adders.17 Brockman, ND, 2004

 Carry-Bypass Adder (cont.)

Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15

Setup tsetup Setup Setup Setup
tbypass

Carry Carry Carry Carry

propagation propagation propagation propagation

Sum Sum Sum tsum Sum

M bits

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

CSE/EE 462 L14 Adders.18 Brockman, ND, 2004

 Carry Ripple versus Carry Bypass

tp
ripple adder

bypass adder

4..8
N

CSE/EE 462 L14 Adders.19 Brockman, ND, 2004

 Carry-Skip Adder Extensions
 Variable block sizes
 A carry that is generated in, or absorbed by, one of the inner
blocks travels a shorter distance through the skip blocks, so can
have bigger blocks for the inner carries without increasing the
overall delay

Cout Cin

 Multiple levels of skip logic

Cout Cin

skip level 1
AND of the
skip level 2 first level skip
signals (BP’s)
CSE/EE 462 L14 Adders.20 Brockman, ND, 2004
 Carry-Skip Adder Comparisons

70

60

50

40 RCA
CSkA
30 B=6 VSkA
B=5
20 B=4
B=2 B=3
10

0
8 bits 16 bits 32 bits 48 bits 64 bits

CSE/EE 462 L14 Adders.21 Brockman, ND, 2004

 Carry-Select Adder

Setup

P,G

"0" "0" Carry Propagation

"1" "1" Carry Propagation

Co,k-1 Multiplexer Co,k+3

Carry Vector

Sum Generation

CSE/EE 462 L14 Adders.22 Brockman, ND, 2004

 Carry Select Adder: Critical Path

Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15

Setup Setup Setup Setup

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7 Co,11 Co,15

Sum Generation Sum Generation Sum Generation Sum Generation

S0–3 S4–7 S8–11 S

CSE/EE 462 L14 Adders.23 Brockman, ND, 2004

 Linear Carry Select

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

(1)

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
(1)

"1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(5) (5) (5) (5) (5)
(6) (7) (8)
Multiplexer Multiplexer Multiplexer Multiplexer
Ci,0
(9)

Sum Generation Sum Generation Sum Generation Sum Generation

S0-3 S 4-7 S8-11 S 1 2-15 (10)

CSE/EE 462 L14 Adders.24 Brockman, ND, 2004

 Square Root Carry Select

Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19

Setup Setup Setup Setup

(1)

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
(1)

"1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(3) (3) (4) (5) (6) (7)
(4) (5) (6) (7)
Multiplexer Multiplexer Multiplexer Multiplexer Mux
C i,0
(8)
Sum Generation Sum Generation Sum Generation Sum Generation Sum

S0-1 S2-4 S5-8 S9-13 S14-19 (9)

CSE/EE 462 L14 Adders.25 Brockman, ND, 2004

 Adder Delays - Comparison

50

40 Ripple adder
tp (in unit delays)

30

Linear select
20

10
Square root select

0
0 20 40 60
N

CSE/EE 462 L14 Adders.26 Brockman, ND, 2004

 LookAhead - Basic Idea

A A1, B1 ••• AN-1, BN-1

Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1

S0 S1 ••• SN-1

C o k = f A k B k Co  k – 1  = Gk + P k Co  k – 1

CSE/EE 462 L14 Adders.27 Brockman, ND, 2004

 Look-Ahead: Topology

Expanding Lookahead equations: VDD

C o k = Gk + Pk Gk – 1 + Pk – 1 Co  k – 2 
G2

G1
All the way:
G0
C o k = Gk + Pk  Gk – 1 + P k – 1  + P1  G0 + P0 Ci  0   
Ci,0
Co,3

P0

P1

P2

P3

CSE/EE 462 L14 Adders.28 Brockman, ND, 2004

 Parallel Prefix Adders (PPAs)
 Define carry operator € on (G,P) signal pairs
(G’’,P’’) (G’,P’)
G’’
G’
€ !G
where
G = G’’  P’’G’ P’’
(G,P)
P = P’’P’

 € is associative, i.e.,
[(g’’’,p’’’) € (g’’,p’’)] € (g’,p’) = (g’’’,p’’’) € [(g’’,p’’) € (g’,p’)]

€ €

€ €

CSE/EE 462 L14 Adders.29 Brockman, ND, 2004

 PPA General Structure
 Given P and G terms for each bit position, computing all
the carries is equal to finding all the prefixes in parallel
(G0,P0) € (G1,P1) € (G2,P2) € … € (GN-2,PN-2) € (GN-1,PN-1)
 Since € is associative, we can group them in any order
 but note that it is not commutative

Pi, Gi logic (1 unit delay)  Measures to consider

Ci parallel prefix logic tree
(1 unit delay per level)
Si logic (1 unit delay)
 number of € cells
 tree cell depth (time)
 tree cell area
 cell fan-in and fan-out
 max wiring length
 wiring congestion
 delay path variation (glitching)

CSE/EE 462 L14 Adders.30 Brockman, ND, 2004

 Brent-Kung PPA

G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0

p15 p14 p13 P12 p11 P10 p9 P8 P7 P6 P5 P4 P3 p2 P1 P0 Cin

€ € € € € € € € €

T = log2N
Parallel Prefix Computation

€ € € €

A = 2log2N
€ €

€ €

T = log2N - 2
€ € €

€ € € € € € €

C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1

A = N/2

CSE/EE 462 L14 Adders.32 Brockman, ND, 2004

 Kogge-Stone PPF Adder
G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Cin

€ € € € € € € € € € € € € € € €
Parallel Prefix Computation

€ € € € € € € € € € € € € €

A = log2N
T = log2N
€ € € € € € € € € € € €

€ € € € € € € €

C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1

A=N
Tadd = tsetup + log2N t€ + tsum
CSE/EE 462 L14 Adders.33 Brockman, ND, 2004
 More Adder Comparisons

70

60

50
RCA
40
CSkA
30 VSkA
KS PPA
20

10

0
8 bits 16 bits 32 bits 48 bits 64 bits

CSE/EE 462 L14 Adders.34 Brockman, ND, 2004