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LaunchPad
Version 1.0
Agenda
Portfolio …
TI Embedded Processing Portfolio
TI Embedded Processors
Microcontrollers (MCUs) ARM®-Based Processors Digital Signal Processors (DSPs)
Roadmap …
MSP430 Roadmap
R0 / PC (Program Counter)
R1 / SP (Stack Pointer)
100% code compatible with R2 / CG1
earlier versions R2
R3 R3 / CG2
1MB unified memory map R4 R4
R5 R5
No paging
20-bit Address
R6 R6
16-bit Data
Extended addressing modes R7 R7
R8
Page-free 20-bit reach R8
R9 R9
Improved code density R10 R10
Faster execution R11 R11
R12
Full tools support through R12
R13 R13
IAR and CCS R14 R14
R15 R15
Memory Map …
Memory Map
x2231 shown
Flash programmable via JTAG or 0FFFFh Interupt Vector Table
In-System (ISP) 0FFE0h
FFDFh Flash/ROM
ISP down to 2.2V. Single-byte or
Word 0F800h
Interruptible ISP/Erase
Main memory: 512 byte segments 010FFh Information
(0-n). Erasable individually or all 01000h Memory
Information memory: 64 byte
segments (A-D)
Section A contains device-specific 027Fh RAM
calibration data and is lockable 0200h
Programmable Flash Memory 01FFh 16-bit
Peripherals
Timing Generator 0100h
0FFh 8-bit
Peripherals
010h
0Fh 8-bit Special Function
Registers
0h
Peripherals …
Value Line Peripherals
10-bits of General Purpose I/O
8-bits on port P1 and 2-bits on port P2
Independently programmable
Any combination of input, output, and interrupt (edge
selectable) is possible
Read/write access to port-control registers is supported by
all instructions
Each I/O has an individually programmable pull-up/pull-
down resistor
16-bit Timer_A2
2 capture/compare registers
Extensive interrupt capabilities
WDT+ Watchdog Timer
Also available as an interval timer
Brownout Reset
Provides correct reset signal during power up and down
Power consumption included in baseline current draw
Peripherals …
Value Line Peripherals
Universal Serial Interface (USI)
Basic hardware for SPI and I2C
Master or Slave modes
Programmable clock
Comparator_A+
Inverting and non-inverting inputs
Selectable RC output filter
Output to Timer_A2 capture input
Interrupt capability
8 Channel/10-bit 200 ksps SAR ADC
8 external channels (device dependent)
Voltage and Internal temperature sensors
Programmable reference
Direct transfer controller send results to conversion
memory with CPU intervention
Interrupt capable Board …
LaunchPad Development Board
USB Emulator
Connection
Embedded Emulation
Crystal Pads
Chip Pinouts Part and Socket
Agenda …
Agenda
License manager
Support for all TI MCUs
Only $495 for MCU license
FREE 16KB-limited edition
IAR …
IAR Kickstart
4kB Compiler
Supports all MSP430
variants
Assembler/Linker
Editor
Debugger
CCS Details …
Code Composer Studio: IDE
List of files:
Source (C, assembly)
Libraries
Linker command files
Project settings:
Build options (compiler,
Linker, assembler, etc)
Build configurations
Creating a New CCSv4 Project
3
File New CCS Project
Lab …
Lab2: Code Composer Studio
• Lab
•Re-create temperature sense demo
•Program part and test
•Optional
• Add microcrystal to board
• Program part to test crystal
Agenda …
Agenda
xxxxx …
System State at Reset
At power-up (PUC), the brownout circuitry holds device in reset until
Vcc is above hysteresis point
RST/NMI pin is configured as reset
I/O pins are configured as inputs
Clocks are configured
Peripheral modules and registers are initialized (see user guide for
specifics)
Status register (SR) is reset
Watchdog timer powers up active in watchdog mode
Program counter (PC) is loaded with address contained at reset vector
location (0FFFEh). If the reset vectors content is 0FFFFh the device
will be disabled for minimum power consumption
S/W Init …
Software Initialization
Clock System …
Clock System
Very Low Power/Low Frequency VLO
Oscillator (VLO)*
4 – 20kHz (typical 12kHz) Min. Puls ACLK
Filter Peripherals
500nA standby
0.5%/°C and 4%/Volt drift
Not in ’21x1 devices OSC_Fault MCLK
CPU
Crystal oscillator (LFXT1)
Programmable capacitors
Failsafe OSC_Fault
16MHz SMCLK
DCO Peripherals
Minimum pulse filter
Digitally Controlled Oscillator
(DCO) On PUC, MCLK and SMCLK are
sourced from DCOCLK at ~1.1 MHz.
<1µs 0-to-16MHz ACLK is sourced from LFXT1CLK in
+ 3% tolerance
LF mode with an internal load
capacitance of 6pF. If LFXT1 fails,
Factory calibration in Flash ACLK defaults to VLO.
TAR
fVLO = 8MHz/Counts
CCRx
WDT failsafe …
Watchdog Timer Failsafe Operation
SMCLK 1
ACLK 1
WDTSSEL A EN WDTHOLD
Init code …
Lab3: Initialization
Agenda …
Agenda
ADC10 …
Fast Flexible ADC10
AUTO
Data2
ADC Data1
DTC Data0
Data2
//
// Software
Software //
// Autoscan
Autoscan ++ DTC
DTC
Res[pRes++]
Res[pRes++] == ADC10MEM;
ADC10MEM; _BIS_SR(CPUOFF);
_BIS_SR(CPUOFF);
ADC10CTL0 &= ~ENC;
ADC10CTL0 &= ~ENC;
if
if (pRes
(pRes << NR_CONV)
NR_CONV)
{{
CurrINCH++;
Fully Automatic
CurrINCH++;
ifif (CurrINCH
(CurrINCH ==== 3)
3)
CurrINCH =
CurrINCH = 0;0;
ADC10CTL1
ADC10CTL1 &=&= ~INCH_3;
~INCH_3;
ADC10CTL1 |= CurrINCH;
ADC10CTL1 |= CurrINCH;
ADC10CTL0
ADC10CTL0 |=|= ENC+ADC10SC;
ENC+ADC10SC;
}}
70 Cycles / Sample
LAB …
Lab4: ADC
Agenda …
Agenda
Timer Architecture …
Timer_A2 Features
Asynchronous 16-bit
timer/counter
Continuous, up-down,
up count modes
Two capture/compare
registers
PWM outputs
Two interrupt vectors
for fast decoding
Vector Table …
Vector Table
Interrupt Source Interrupt System Word Address Priority
Flag Interrupt
Power-up PORIFG
External Reset RSTIFG
Watchdog Timer+ WDTIFG Reset 0FFFEh 31
Flash key violation KEYV (highest)
PC out-of-range
NMI NMIIFG Non-maskable
Oscillator Fault OFIFG Non-maskable 0FFFCh 30
Flash memory access ACCVIFG Non-maskable
violation
0FFFAh 29
0FFF8h 28
0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer_A2 TACCR0 CCIFG maskable 0FFF2h 25
ISR Coding …
ISR Coding
#pragma vector=WDT_VECTOR
__interrupt void WDT_ISR(void)
{
IE1 &= ~WDTIE; // disable interrupt
IFG1 &= ~WDTIFG; // clear interrupt flag
WDTCTL = WDTPW + WDTHOLD; // put WDT back in hold state
BUTTON_IE |= BUTTON; // Debouncing complete
}
#pragma vector - the following function is an ISR for the listed vector
_interrupt void - indentifies ISR name
No special return required
LAB …
Lab5: Timer and Interrupts
• Configure Timer_A2
• Alter code to operate using interrupts
• Build and test
Agenda …
Agenda
Operation …
Low-Power Operation
Power-efficient MSP430 apps:
Minimize instantaneous current draw
Maximize time spent in low power modes
The MSP430 is inherently low-power, but your
design has a big impact on power efficiency
Proper low-power design techniques make the
difference
Pin Muxing …
Pin Muxing
LAB …
Lab6: Low-Power Modes
Agenda …
Agenda
USI …
Universal Serial Interface
Protocols …
Protocols
SPI SCLK
MOSI
SPI SPI
Serial Peripheral Interface Master MISO
Slave
SSN
Single Master/Single Slave
Vdd
R R
I2C SDA
SCL
Inter-Integrated Circuit
Interface C DAC ADC C
Single Master/Multiple Slaves Master Slave Slave Slave
HI, LO, IN
LAB …
Lab7: Serial Communication