Topic 9.4 & 9.

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Fizzah Attique
Roll # 20
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9.4 Multiplication

 More complicated than addition

– A straightforward implementation will
involve shifts and adds
 More complex operation can lead to
– More area (on silicon) and/or
– More time (multiple cycles or longer
clock cycle time)
 Let’s begin from a simple,
straightforward method
Straightforward
Algorithm
01010010 (multiplicand)
x 01101101 (multiplier)
01010010
00000000 4
01010010
01010010
00000000
01010010
01010010
00000000
010001011101010
Register Configuration

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Multiplication Example

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Sign Extension

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Afshan Bashir 8

Roll # 29
9.4.1 Booth Algorithm

▹ Booth’s algorithm is a
multiplication algorithm that 9
multiplies two signed binary
numbers in 2’s compliment
notation.
Points to Remember

▹ You will need twice as many bits in

your product as you have in your 10
original two operands.
▹ The leftmost bit of your operands
(both your multiplicand and
multiplier) is a SIGN bit, and
cannot be used as part of the
value.
To Begin:

▹ Decide which operand will be the

multiplier and which will be the 11
multiplicand
▹ Convert both operands to two's
complement representation
▹ Begin with a product that consists
of the multiplier
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Flow Chart 13
Hifsa Khan 14

Roll # 23
Example of Booth
Algorithm

▹ 1. 2*3 solve it using booth

algorithm. 15

▹ 2. 2*-3 solve it using booth

algorithm
Sadia Jalil 16

Roll # 16
9.5 Fast Multiplication

▹ The first technique guarantees

that the maximum number of 17
summands (versions of the
multiplicand)that must be added is
n/2 for n-bit operands.
▹ The second technique leads to
adding the summands in parallel.
1. Bit Pair Recording of
Multipliers

▹ Bit-pair recoding is the product of the

multiplier results in using at most one
summand for each pair of bits in the 18

multiplier. It is derived directly from the

Booth algorithm. Grouping the Booth-
recoded multiplier bits in pairs will
decrease the multiplication only by
summands.
Example

▹ 13 * 6 using bit pair recording of

Multipliers. 19
2. Carry-Save Addition of
Summands

▹ Multiplication requires the

addition of several summands. A 20
technique called carry-save
addition (CSA) can be used to
speed up the process.
Ripple Carry Array

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Carry Save Array

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Sara Bashir 23

Roll # 11
3. Summand Addition Tree
using 3-2 Reducers

▹ A more significant reduction in

delay can be achieved when 24
dealing with longer operands
▹ We can group the summands in
threes and perform carry-save
addition on each of these groups
in parallel in one full-adder delay.
Example

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4. Summand Addition Tree
using 4-2 Reducers

▹ A more regularly structured tree

can be obtained by using 4-2 26
reducers, especially for the case
in which the number of summands
to be reduced is a power of 2.
▹ This is the usual case for the
multiplication operation in the
ALU of a processor.
Diagram

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Conclusion:
▹ Bit-pair recoding of the multiplier,
derived from the Booth algorithm, can be
used to initially reduce the number of 28
summands by a factor of two.
▹ The resulting summands can then be
reduced to two in a reduction tree with a
relatively small number of reduction
levels.
▹ The final product can be generated by an
addition operation.
THANKS!
Any queries?
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