Digital Integrated Circuits: A Design Perspective

Digital Integrated
Circuits
A Design Perspective
Designing Sequential
Logic Circuits
© Digital Integrated Circuits2nd

Sequential Circuits
Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Registers
Q D
CLK
2 storage mechanisms
• positive feedback
• charge-based

Sequential Circuits
Naming Conventions
 In our text:
 a latch is level sensitive
 a register is edge-triggered
 There are many different naming
conventions
 For instance, many books call edge-
triggered elements flip-flops
 This leads to confusion however

Sequential Circuits
Latch versus Register
 Latch  Register
stores data when stores data when
clock is low clock rises
D Q D Q
Clk Clk
Clk Clk
D D
Q Q

Sequential Circuits
Latches

Sequential Circuits
Latch-Based Design
• N latch is transparent • P latch is transparent
when f = 0 when f = 1
f
N P
Logic
Latch Latch
Logic

Sequential Circuits
Timing Definitions
CLK
t Register
tsu thold D Q
D DATA CLK
STABLE t
tc - q
Q DATA
STABLE t

Sequential Circuits
Characterizing Timing
tD - Q
D Q D Q
Clk Clk
tC - Q tC - Q
Register Latch

Sequential Circuits
Maximum Clock Frequency
f
FF’s
LOGIC Also:
tcdreg + tcdlogic > thold
tp,comb
tcd: contamination delay =
minimum delay
tclk-Q + tp,comb + tsetup = T

Sequential Circuits
Positive Feedback: Bi-Stability
V o1 Vi2
1
o 1
o
V V
52
Vi
V i1 V o2
A
V i 2 = V o1
1
Vo
52 C
Vi
B
V i 1 = V o2

Sequential Circuits
Meta-Stability
Gain should be larger than 1 in the transition region

Sequential Circuits
Writing into a Static Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK
Q D D
CLK
CLK
D
CLK
Forcing the state
Converting into a MUX (can implement as NMOS-only)

Sequential Circuits
Mux-Based Latches
Negative latch Positive latch
(transparent when CLK= 0) (transparent when CLK= 1)
Q 0 Q
1
D 0 D 1
CLK CLK
Q  Clk  Q  Clk  In Q  Clk  Q  Clk  In

Sequential Circuits
Mux-Based Latch
CLK
CLK
CLK

Sequential Circuits
Mux-Based Latch
CLK
QM
CLK
QM
CLK
CLK
NMOS only Non-overlapping clocks

Sequential Circuits
Master-Slave (Edge-Triggered)
Register
Two opposite latches trigger on edge

Also called master-slave latch pair

Sequential Circuits
Master-Slave Register
Multiplexer-based latch pair
I2 T2 I3 I5 T4 I6 Q
QM
D I1 T1 I4 T3
CLK

Sequential Circuits
Clk-Q Delay
2.5
CLK
1.5
D
tc - q(lh) tc - q(hl)
Volts Q
0.5
2 0.5
0 0.5 1 1.5 2 2.5
time, nsec

Sequential Circuits
Setup Time

Sequential Circuits
Reduced Clock Load
Master-Slave Register
CLK CLK
D T1 I1 T2 I3 Q
I2 I4
CLK CLK

Sequential Circuits
Avoiding Clock Overlap
CLK X CLK
Q
A
D
B
CLK CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs

Sequential Circuits
Overpowering the Feedback Loop ─
Cross-Coupled Pairs
NOR-based set-reset
S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
0 1 0 1
Q
R 1 1 0 0
Forbidden State

Sequential Circuits
Cross-Coupled NAND
Added clock
Cross-coupled NANDs VDD
S M2 M4
Q
Q
Q
Q CLK M6 M8 CLK
R M1 M3
S M5 M7 R
This is not used in datapaths any more,

but is a basic building memory cell

Sequential Circuits
Sizing Issues
2.0 3
Q S
1.5
2 W = 0.5 m m
Q (Volts)
W = 0.6 m m
Volts
1.0
W = 0.7 m m
1
0.5 W = 0.8 m m
W = 0.9 m m
W = 1m m
0.0 0
2.0 2.5 3.0 3.5 4.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
W/L 5 and 6 time (ns)
(a) (b)
Output voltage dependence Transient response

on transistor width

Sequential Circuits
Storage Mechanisms
Static Dynamic (charge-based)
CLK
CLK
D Q
Q
CLK
CLK
D
CLK

Sequential Circuits
Making a Dynamic Latch Pseudo-Static
CLK
D D
CLK

Sequential Circuits
More Precise Setup Time

Sequential Circuits
Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN
TG1
Inv2 Clk-Q Delay
D1 SM QM
D
Inv1
CP
TClk-Q
TSetup-1 Time
Data Clock
TSetup-1
Time
t=0

Sequential Circuits
CN
TG1
Inv2 Clk-Q Delay
D1 SM QM
D
Inv1
CP
TClk-Q
TSetup-1 Time
Data Clock
TSetup-1
Time
t=0

Sequential Circuits
CN
TG1
Inv2 Clk-Q Delay
D1 SM QM
D
Inv1
CP
TClk-Q
TSetup-1 Time
Data Clock
TSetup-1
Time
t=0

Sequential Circuits
CN
TG1
Inv2 Clk-Q Delay
D1 SM QM
D
Inv1
TClk-Q
CP
TSetup-1 Time
Data Clock
TSetup-1
Time
t=0

Sequential Circuits
CN
TG1
Inv2 Clk-Q Delay
D1 SM QM TClk-Q
D
Inv1
CP
TSetup-1 Time
Data Clock
TSetup-1
Time
t=0

Sequential Circuits
Hold-1 case
CN
TG1 Clk-Q Delay

Inv2
D1 SM QM
D
Inv1
0
CP
TClk-Q
THold-1
Time
Clock Data
THold-1
Time
t=0

Sequential Circuits
Hold-1 case
CN
TG1 Clk-Q Delay

Inv2
D1 SM QM
D
Inv1
0
CP
TClk-Q
THold-1
Time
Clock Data
THold-1
Time
t=0

Sequential Circuits
Hold-1 case
CN
TG1 Clk-Q Delay

Inv2
D1 SM QM
D
Inv1
0
CP TClk-Q
THold-1
Time
Clock Data
THold-1
Time
t=0

Sequential Circuits
Hold-1 case
CN
TG1 Clk-Q Delay

Inv2
D1 SM QM
D
Inv1 TClk-Q
0
CP
THold-1
Time
Clock Data
THold-1
Time
t=0

Sequential Circuits
Hold-1 case
CN
TG1 Clk-Q Delay

Inv2 TClk-Q
D1 SM QM
D
Inv1
0
CP
THold-1
Time
Clock Data
THold-1 
Time
t=0

Sequential Circuits
Other Latches/Registers: C2MOS
VDD VDD
M2 M6
CLK M4 CLK M8
X
D Q
CL1 CL2
CLK M3 CLK M7
M1 M5
Master Stage Slave Stage
“Keepers” can be added to make circuit pseudo-static

Sequential Circuits
Insensitive to Clock-Overlap
VDD VDD VDD VDD
M2 M6 M2 M6
0 M4 0 M8
X X
D Q D Q
1 M3 1 M7
M1 M5 M1 M5
(a) (0-0) overlap (b) (1-1) overlap

Sequential Circuits
Pipelining
REG
REG
a a
REG
REG
REG
REG
log Out CLK log Out
CLK
REG
REG
b CLK b CLK CLK CLK
CLK CLK
Reference Pipelined

Sequential Circuits
Other Latches/Registers: TSPC
VDD VDD VDD VDD
Out
In CLK CLK In CLK CLK
Out
Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)

Sequential Circuits
Including Logic in TSPC
VDD VDD VDD VDD
In1 In2
PUN
Q Q
In CLK CLK CLK CLK
PDN In1
In2
Example: logic inside the latch

AND latch

Sequential Circuits
TSPC Register
VDD VDD VDD
CLK Q
M3 M6 M9
Y
Q
D CLK X CLK
M2 M5 M8
CLK
M1 M4 M7

Sequential Circuits
Pulse-Triggered Latches
An Alternative Approach
Ways to design an edge-triggered sequential cell:
Master-Slave Pulse-Triggered
Latches Latch
L1 L2 L
Data Data
D Q D Q D Q
Clk Clk Clk Clk

Clk

Sequential Circuits
Pulsed Latches
VDD VDD
M3 M6 VDD
CLK
Q
D CLKG CLKG MP CLKG
M2 M5
X
MN
M1 M4
(a) register (b) glitch generation
CLK
CLKG
(c) glitch clock

Sequential Circuits
Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
CLK P1 P3
x Q
M6
M3
D P2 M5
M2
M4
M1 CLKD

Sequential Circuits
Hybrid Latch-FF Timing

Sequential Circuits
Latch-Based Pipeline

Sequential Circuits
Non-Bistable Sequential Circuits─
Schmitt Trigger
Vou t V OH
In Out
•VTC with hysteresis V OL
•Restores signal slopes
VM– VM+ Vi n

Sequential Circuits
Noise Suppression using Schmitt
Trigger

Sequential Circuits
CMOS Schmitt Trigger
VDD
M2 M4
Vin X Vout
M1 M3
Moves switching threshold

of the first inverter

Sequential Circuits
Schmitt Trigger Simulated VTC
2.5 2.5
2.0 2.0
1.5 VM1 1.5
(V)
X1.0 VM2 (V)
x1.0
k=1
V V k=3
k=2
0.5 0.5
k=4
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
Vin (V) Vin (V)
Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the
PMOS device M4. The width is k* 0.5m m.

Sequential Circuits
CMOS Schmitt Trigger (2)
VDD
M4
M6
M3
In Out
M2
X M5
VDD
M1

Sequential Circuits
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator

Sequential Circuits
Transition-Triggered Monostable
In
DELAY
Out
td td

Sequential Circuits
Monostable Trigger (RC-based)
VDD
In R
A B Out
(a) Trigger circuit.

C
In
B VM
(b) Waveforms.
Out
t
t1 t2

Sequential Circuits
Astable Multivibrators (Oscillators)
0 1 2 N-1
Ring Oscillator
simulated response of 5-stage oscillator

Sequential Circuits
Relaxation Oscillator
Out1
Out2
I1 I2
R C
Int
T = 2 (log3) RC

Sequential Circuits
Voltage Controller Oscillator (VCO)
Schmitt Trigger
VD D VDD
restores signal slopes
M6 M4
M2
In
M1
Iref Iref
Vcontr M3
M5 Current starved inverter
6
tpH L (nsec)
propagation delay as a function

0.0
0.5 1.5 2.5 of control voltage
V co ntr (V)

Sequential Circuits
Differential Delay Element and VCO
V o2 V o1 v3
v1
in 1 in 2
v2
v
4
V ctrl
delay cell two stage VCO

3.0
V1 V2 V3 V4
2.5
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5 1.5 2.5 3.5
time (ns)
simulated waveforms of 2-stage VCO

Sequential Circuits

Digital Integrated Circuits: A Design Perspective

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Integrated Circuits: A Design Perspective

Uploaded by

Copyright:

Available Formats

Digital Integrated

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

Gain should be larger than 1 in the transition region

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

Q  Clk  Q  Clk  In Q  Clk  Q  Clk  In

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

NMOS only Non-overlapping clocks

© Digital Integrated Circuits2nd

Two opposite latches trigger on edge

© Digital Integrated Circuits2nd

Multiplexer-based latch pair

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

This is not used in datapaths any more,

© Digital Integrated Circuits2nd

Output voltage dependence Transient response

© Digital Integrated Circuits2nd

Static Dynamic (charge-based)

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

© Digital Integrated Circuits2nd

TG1 Clk-Q Delay

© Digital Integrated Circuits2nd

TG1 Clk-Q Delay

© Digital Integrated Circuits2nd

TG1 Clk-Q Delay

© Digital Integrated Circuits2nd

TG1 Clk-Q Delay

© Digital Integrated Circuits2nd

TG1 Clk-Q Delay

© Digital Integrated Circuits2nd

Master Stage Slave Stage

“Keepers” can be added to make circuit pseudo-static

© Digital Integrated Circuits2nd

(a) (0-0) overlap (b) (1-1) overlap

© Digital Integrated Circuits2nd

b CLK b CLK CLK CLK

© Digital Integrated Circuits2nd

In CLK CLK In CLK CLK

Positive latch Negative latch

© Digital Integrated Circuits2nd

In CLK CLK CLK CLK

Example: logic inside the latch