REE-602: MICROPROCESSORS

UNIT-3
B.Tech. EN-5TH SEMESTER
8086 MICROPROCESSOR
Intel 8086
Intel 8086 was launched in
1978.
It was the first 16-bit
microprocessor.
This microprocessor had
major improvement over
the execution speed of
8085.
It is available as 40-pin Dual-
Inline-Package (DIP).
Intel 8086
• It is available in three
versions:
– 8086 (5 MHz)
– 8086-2 (8 MHz)
– 8086-1 (10 MHz)

• It consists of 29,000
transistors.
Intel 8086
It has a 16 line data bus.
And 20 line address bus.
It could address up to 1
MB of memory.
It has more than 20,000
instructions.
It supports multiplication
and division.
 Block Diagram of Intel 8086
General Segment
Purpose Registers
Registers, &
Pointers & Instruction
Index Pointer
Registers

Address Lines
Data Lines
BHE/S7, RD,
WR,
INTA, ALE,
DT/R,
DEN

CLK
VCC Control
GND Lines
MN / MX
 Block Diagram of Intel 8086
• Intel 8086 contains two independent
functional units:

Bus Interface Unit (BIU)

Execution Unit (EU)
 Bus Interface Unit
• Bus Interface Unit contains:

Segment Registers
Instruction Pointer
6-Byte Instruction Queue
 Execution Unit
 Execution Unit contains:
General Purposes Registers
Stack Pointer
Base Pointer
Index Registers
ALU
Flag Register
Instruction Decoder
Timing & Control Unit
 Functions of Bus Interface Unit
It handles transfer of data and addresses between the
processor and memory / IO.
It reads data from memory and I/O devices.
It writes data to memory and I/O devices.
It computes and sends out addresses.
It fetches instruction codes.
It stores fetched instruction codes in a FIFO register
called QUEUE.
 Instruction Queue
To increase the execution speed, BIU fetches as
many as six instruction bytes ahead to time from
memory.
All six bytes are then held in first-in-first-out 6-
byte register called instruction queue.
Then all bytes are given to EU one by one.
This pre-fetching operation of BIU may be in
parallel with execution operation of EU, which
improves the execution speed of the instruction.
 Functions of Execution Unit
It receives opcode of an instruction from the QUEUE.
It decodes it and then executes it.
It tells BIU where to fetch the instructions or data from.
It contains the control circuitry to perform various
internal operations.
It has 16-bit ALU, which can perform arithmetic and
logical operations on 8-bit as well as 16-bit data.
 Pipelining
While EU executes instructions, BIU fetches
instructions from memory and stores them in
the QUEUE.
BIU and EU operate in parallel independent of
each other.
This type of overlapped operation of the
functional units of a MP is called Pipelining.
 Registers of Intel 8086
• Intel 8086 contains following registers:
General Purpose Registers
Pointer and Index Registers
Segment Registers
Instruction Pointer
Status Flags
 General Purpose Registers
• There are four 16-bit general purpose
registers:
AX
BX
CX
DX
 General Purpose Registers
• Each of these 16-bit registers are further
subdivided into two 8-bit registers.

AX AH AL
BX BH BL
CX CH CL
DX DH DL
 General Purpose Registers
AX Register: AX register is also known as accumulator
register that stores operands for arithmetic operation
like divided, rotate.
BX Register: This register is mainly used as a base
register. It holds the starting base location of a memory
region within a data segment.
CX Register: It is defined as a counter. It is primarily
used in loop instruction to store loop counter.
DX Register: DX register is used to contain I/O port
address for I/O instruction.
 Pointer and Index Registers
• Following four registers are under this
category:
Stack Pointer (SP)
Base Pointer (BP)
Source Index (SI)
Destination Index (DI)
 Pointer and Index Registers
Stack Pointer (SP):
The function of SP is same as the function of SP in
Intel 8085.
It stores the address of top element in the stack.

BP, SI & DI are used in memory address

computation. (Is discussed in ‘Memory Segmentation of 8086’
slide)
 Segment Registers
• There are four segment registers in Intel 8086:
Code Segment Register (CS)
Data Segment Register (DS)
Stack Segment Register (SS)
Extra Segment Register (ES)
 Segment Registers
• In 8086, memory is divided into four
segments:
Code Segment
Data Segment
Stack Segment
Extra Segment
 Segment Registers
A segment register points to the starting address
of a memory segment.
For e.g.:
The code segment register points to the starting
address of the code segment.
The data segment register points to the starting
address of the data segment, and so on.
The maximum capacity of a segment may be up
to 64 KB.
Segment Registers
 Segment Registers
The instructions of 8086 specify 16-bit
address.
But the actual physical addresses are of 20-bit.
Therefore, they are calculated using the
contents of the segment registers and the
effective memory address.
 Instruction Pointer
The Instruction Pointer (IP) in 8086 acts as a Program
Counter.
It points to the address of the next instruction to be
executed.
Its content is automatically incremented when the
execution of a program proceeds further.
The contents of the IP and Code Segment Register are
used to compute the memory address of the
instruction code to be fetched.
This is done during the Fetch Cycle.
 Status Flags
• Status Flags determines the current state of
the accumulator.
• They are modified automatically by CPU after
mathematical operations.
• This allows to determine the type of the
result.
 Status Flags
8086 has 16-bit status register.
It is also called Flag Register or Program Status
Word (PSW).
There are nine status flags and seven bit positions
remain unused.

Flag Register of 8086

 Status Flags
• 8086 has 9 flags and they are divided into two
categories:

Condition Flags
Control Flags
 Status Flags
• Following are the nine flags:

Condition Flags Control Flags

1. Carry Flag 1. Trap Flag
2. Auxiliary Carry Flag 2. Interrupt Flag
3. Zero Flag 3. Directional Flag
4. Sign Flag
5. Parity Flag
6. Overflow Flag
 Condition Flags
 Condition flags represent result of last arithmetic or logical
instruction executed. Conditional flags are as follows:

 Carry Flag (CF): This flag is set if there is a carry / borrow after an
integer arithmetic.

 Auxiliary Carry Flag (AF): If an operation performed in ALU

generates a carry / borrow from lower nibble (i.e. D0 – D3) to upper
nibble (i.e. D4 – D7), then AF is set. It is used in BCD Addition.

 Parity Flag (PF): This flag is used to indicate the parity of result. If
the result contains even number of 1’s, the Parity Flag is set and for
odd number of 1’s, the Parity Flag is reset.
 Condition Flags
Zero Flag (ZF): It is set; if the result of arithmetic
or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign
of number is indicated by MSB bit. If the result of
operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed
numbers are added or subtracted. An OF indicates
that the result has exceeded the capacity of
machine.
 Control Flags
Control flags are set or reset deliberately to
control the operations of the execution unit.
Control flags are as follows:
Trap Flag (TP):
It is used for single step control.
It allows user to execute one instruction of a program
at a time for debugging.
When trap flag is set, program can be run in single step
mode.
 Control Flags
Interrupt Flag (IF):
It is an interrupt enable / disable flag.
If it is set, the INTR interrupt of 8086 is enabled
and if it is reset then INTR is disabled.
It can be set by executing instruction STI and can
be cleared by executing CLI instruction.
 Control Flags
Directional Flag (DF):
It is used in string operation.
If it is set, string bytes are accessed from higher
memory address to lower memory address.
When it is reset, the string bytes are accessed from
lower memory address to higher memory address.
It is set with STD instruction and cleared with CLD
instruction.
Pin Diagram of Intel 8086
 AD0 – AD15
Pin 16-2, 39 (Bi-directional)
• These lines are multiplexed bi-
directional address/data bus.
• During T1, they carry lower order
16-bit address.
• In the remaining clock cycles, they
carry 16-bit data.
• AD0-AD7 carry lower order byte of
data.
• AD8-AD15 carry higher order byte
of data.
 A19/S6, A18/S5, A17/S4, A16/S3
Pin 35-38 (Unidirectional)

• These lines are multiplexed

unidirectional address and
status bus.
• During T1, they carry higher
order 4-bit address.
• In the remaining clock cycles,
they carry status signals.
 BHE / S7
Pin 34 (Output)

• BHE stands for Bus High

Enable.
• BHE signal is used to indicate
the transfer of data over higher
order data bus (D8 – D15).
• 8-bit I/O devices use this signal.
• It is multiplexed with status pin
S7 .
 RD (Read)
Pin 32 (Output)

• It is a read signal used for

read operation.
• It is an output signal.
• It is an active low signal.
 READY
Pin 22 (Input)

• This is an acknowledgement
signal from slower I/O devices
or memory.
• It is an active high signal.
• When high, it indicates that the
device is ready to transfer data.
• When low, then
microprocessor is in wait state.
 RESET
Pin 21 (Input)

• It is a system reset.
• It is an active high signal.
• When high, microprocessor
enters into reset state and
terminates the current activity.
• It must be active for at least
four clock cycles to reset the
microprocessor.
 INTR
Pin 18 (Input)

• It is an interrupt request
signal.
• It is active high.
• It is level triggered.
 NMI
Pin 17 (Input)

• It is a non-maskable interrupt
signal.
• It is an active high.
• It is an edge triggered
interrupt.
 TEST
Pin 23 (Input)

• It is used to test the status of

math co-processor 8087.
• The BUSY pin of 8087 is
connected to this pin of
8086.
• If low, execution continues
else microprocessor is in wait
state.
 CLK
Pin 19 (Input)

• This clock input provides the

basic timing for processor
operation.
• It is symmetric square wave
with 33% duty cycle.
• The range of frequency of
different versions is 5 MHz, 8
MHz and 10 MHz.
 VCC and VSS
Pin 40 and Pin 20 (Input)

• VCC is power supply signal.

• +5V DC is supplied through
this pin.
• VSS is ground signal.
 MN / MX
Pin 33 (Input)

• 8086 works in two modes:

– Minimum Mode
– Maximum Mode
• If MN/MX is high, it works in
minimum mode.
• If MN/MX is low, it works in
maximum mode.
 MN / MX
Pin 33 (Input)

• Pins 24 to 31 issue two

different sets of signals.
• One set of signals is issued
when CPU operates in
minimum mode.
• Other set of signals is issued
when CPU operates in
maximum mode.
8286
Pin Description for
Minimum Mode

51
Minimum Mode
 INTA
Pin 24 (Output)

• This is an interrupt
acknowledge signal.
• When microprocessor
receives INTR signal, it
acknowledges the interrupt
by generating this signal.
• It is an active low signal.
 ALE
Pin 25 (Output)

• This is an Address Latch Enable

signal.
• It indicates that valid address is
available on bus AD0 – AD15.
• It is an active high signal and
remains high during T1 state.
• It is connected to enable pin of
latch 8282.
 DEN
Pin 26 (Output)

• This is a Data Enable signal.

• This signal is used to enable
the transceiver 8286.
• Transceiver is used to
separate the data from the
address/data bus.
• It is an active low signal.
 DT / R
Pin 27 (Output)

• This is a Data Transmit/Receive

signal.
• It decides the direction of data
flow through the transceiver.
• When it is high, data is
transmitted out.
• When it is low, data is received
in.
 M / IO
Pin 28 (Output)

• This signal is issued by the

microprocessor to distinguish
memory access from I/O
access.
• When it is high, memory is
accessed.
• When it is low, I/O devices
are accessed.
 WR
Pin 29 (Output)

• It is a Write signal.
• It is used to write data in
memory or output device
depending on the status of
M/IO signal.
• It is an active low signal.
 HLDA
Pin 30 (Output)

• It is a Hold Acknowledge
signal.
• It is issued after receiving the
HOLD signal.
• It is an active high signal.
 HOLD
Pin 31 (Input)

• When DMA controller needs

to use address/data bus, it
sends a request to the CPU
through this pin.
• It is an active high signal.
• When microprocessor
receives HOLD signal, it
issues HLDA signal to the
DMA controller.
Pin Description for
Maximum Mode
Maximum Mode
 QS1 and QS0
Pin 24 and 25 (Output)

• These pins provide the status

of instruction queue.

QS1 QS0 Status

0 0 No operation
0 1 1st byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue
 S0 , S1 , S 2
Pin 26, 27, 28 (Output)

• These status signals indicate

the operation being done by
the microprocessor.
• This information is required
by the Bus Controller 8288.
• Bus controller 8288
generates all memory and
I/O control signals.
 S0 , S1 , S 2
Pin 26, 27, 28 (Output)

S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
 LOCK
Pin 29 (Output)

• This signal indicates that other

processors should not ask CPU
to relinquish the system bus.
• When it goes low, all interrupts
are masked and HOLD request
is not granted.
• This pin is activated by using
LOCK prefix on any instruction.
 RQ/GT1 and RQ/GT0
Pin 30 and 31 (Bi-directional)

• These are Request/Grant pins.

• Other processors request the CPU
through these lines to release the
system bus.
• After receiving the request, CPU
sends acknowledge signal on the
same lines.

• RQ/GT0 has higher priority than

RQ/GT1.
 Memory Segmentation
• The total memory size is divided into
segments of various sizes.
• A segment is just an area in memory.
• The process of dividing memory this way is
called Segmentation.
 Memory Segmentation
• In memory, data is stored as bytes.
• Each byte has a specific address.
• Intel 8086 has 20 lines address bus.
• With 20 address lines, the memory that can be
addressed is 220 bytes.
• 220 = 1,048,576 bytes (1 MB).
• 8086 can access memory with address ranging
from 00000 H to FFFFF H.
 Memory Segmentation
• In 8086, memory has four different types of
segments.
• These are:
– Code Segment
– Data Segment
– Stack Segment
– Extra Segment
 Segment Registers
• Each of these segments are addressed by an
address stored in corresponding segment
register.
• These registers are 16-bit in size.
• Each register stores the base address (starting
address) of the corresponding segment.
• Because the segment registers cannot store
20 bits, they only store the upper 16 bits.
Segment Registers
 Segment Registers
• How is a 20-bit address obtained if there are only 16-bit
registers?
• The answer lies in the next few slides.
• The 20-bit address of a byte is called its Physical Address.
• But, it is specified as a Logical Address.
• Logical address is in the form of:
Base Address : Offset
• Offset is the displacement of the memory location from
the starting location of the segment.
 Example
• The value of Data Segment Register (DS) is
2222 H.
• To convert this 16-bit address into 20-bit, the
BIU appends 0H to the LSBs of the address.
• After appending, the starting address of the
Data Segment becomes 22220H.
 Example (Contd.)
• If the data at any location has a logical address
specified as:
2222 H : 0016 H
• Then, the number 0016 H is the offset.
• 2222 H is the value of DS.
 Example (Contd.)
• To calculate the effective address of the
memory, BIU uses the following formula:
Effective Address = Starting Address of Segment + Offset

• To find the starting address of the segment,

BIU appends the contents of Segment Register
with 0H.
• Then, it adds offset to it.
 Example (Contd.)
• Therefore:
• EA = 22220 H
+ 0016 H
------------
22236 H
 Example (Contd.)
2222 H BYTE – 0 22220 H
DS Register BYTE – 1
BYTE – 2
-
Offset = 0016 H -
-
-
-
Addressed Byte 22236 H
 Max. Size of Segment
• All offsets are limited to 16-bits.
• It means that the maximum size possible for
segment is 216 = 65,535 bytes (64 KB).
• The offset of the first location within the
segment is 0000 H.
• The offset of the last location in the segment
is FFFF H.
Where to Look for the Offset

Segment Offset Registers Function

CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Address in the stack
ES BX, DI, SI Address of destination data
(for string operations)
 Question
• The contents of the following registers are:
 CS = 1111 H
 DS = 3333 H
 SS = 2526 H
 IP = 1232 H
 SP = 1100 H
 DI = 0020 H
• Calculate the corresponding physical addresses for the
address bytes in CS, DS and SS.
 Solution
1. CS = 1111 H
 The base address of the code segment is 11110 H.
 Effective address of memory is given by 11110H + 1232H = 12342H.
2. DS = 3333 H
 The base address of the data segment is 33330 H.
 Effective address of memory is given by 33330H + 0020H = 33350H.
3. SS = 2526 H
 The base address of the stack segment is 25260 H.
 Effective address of memory is given by 25260H + 1100H = 26360H.
8086 Block Diagram

I-10
8086 Programmers Model
8086 Addressing Modes

4
8086 Addressing Modes

1. Register Addressing Mode

2. Immediate Addressing Mode
3. Memory Addressing Mode
4. String Addressing Mode
5. I/O Addressing Mode
6. Implied Addressing Mode
8086 Addressing Modes
1.Register Addressing
Mode

7
Register Addressing Mode

 Data is in register and Instruction Specifies the

perticular register
 E.g
MOV AX,BX
2.Immediate Addressing
Mode

9
2.IMMEDIATE ADDRESSING MODE
 Immediate operand is Constant data contained in an
Instruction
 i.e. The source operand is a part of instruction
instade of register memory
 E.g
MOV CL,02H
3.Memory Addressing
Mode

11
Memory Addressing Mode

3.1 Direct
3.2 Register Indirect
3.3 Based Indexed
3.4 Register Relative
3.5 Relative Based Indexed
Memory Addressing Mode

EFFECTIVE ADDRESS
 The offset of a memory operand is called the
operand’s effective address (EA).
 Is an unsiged 16 bit no. That expresses the
operands distance in byte from the begining of the
segment
 8086 has Base register and Index register
 So EU calculates EA by summing a Displacement,
Content of Base register and Content of Index
register.
Memory Addressing Mode

 Displacement is an 8 or 16 bit no
 It is generally derived from the position of
operand name.
 It’s value is constant.
 Pogrammer may specify either BX or BP is to be
used as Base Register
 Similarly either SI od DI may be specified as Index
Register
Memory Addressing Mode

3.1 DIRECT MEMORY ADDRESSING MODE

15
Memory Addressing Mode

 EA is taken from the displacement field of

instruction.
 PA=This addr. Is added with Seg.Regi*10 H
MOV[1023],AL
Memory Addressing Mode

3.2 REGISTER INDIRECT ADDRESSING MODE

17
Memory Addressing Mode

 EA of may be taken directly from one of the base

register or index register.
 PA=This addr. Is added with Seg.Regi*10 H
MOV[SI],AL
Memory Addressing Mode

3.3 BASED INDEXED ADDRESSING MODE

19
Memory Addressing Mode

 EA is sum of Base register and Index register .

 Both of which are specified by the instruction
 PA=This addr. Is added with Seg.Regi*10 H
MOV[BX+SI],AL
Memory Addressing Mode

3.4 REGISTER RELATIVE ADDRESSING MODE

21
Memory Addressing Mode

 EA is Sum of 8 or 16 bit displacement and contents

of base register or an index register
 PA=This addr. Is added with Seg.Regi*10 H
MOV[BX+1100],AL
Memory Addressing Mode

3.5 RELATIVE BASED INDEXED MODE

23
Memory Addressing Mode

 EA is Sum of a Base register ,an Index Register and

Displacement .
 PA=This addr. Is added with Seg.Regi*10 H
MOV CX,[BX+SI+0400]
 Implied Addressing Mode

• Instructions using this mode have no

operands. In this mode the instruction itself
will specify the data to be operated by the
instruction
• eg:- CLC
• this clears the carry flag to zero.
 Instruction Set of 8086
• An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
• The entire group of instructions that a
microprocessor supports is called Instruction
Set.
• 8086 has more than 20,000 instructions.
 Classification of Instruction Set
• Data Transfer Instructions
• Arithmetic Instructions
• Bit Manipulation Instructions
• Program Execution Transfer Instructions
• String Instructions
• Processor Control Instructions
 Data Transfer Instructions
• These instructions are used to transfer data
from source to destination.
• The operand can be a constant, memory
location, register or I/O port address.
 Data Transfer Instructions
 MOV Des, Src:
 Src operand can be register, memory location or immediate
operand.
 Des can be register or memory operand.
 Both Src and Des cannot be memory location at the same
time.
 E.g.:
 MOV CX, 037A H
 MOV AL, BL
 MOV BX, [0301 H]
 Data Transfer Instructions
 PUSH Operand:
 It pushes the operand into top of stack.
 E.g.: PUSH BX

 POP Des:
 It pops the operand from top of stack to Des.
 Des can be a general purpose register, segment register
(except CS) or memory location.
 E.g.: POP AX
 Data Transfer Instructions
• XCHG Des, Src:
– This instruction exchanges Src with Des.
– It cannot exchange two memory locations directly.
– E.g.: XCHG DX, AX
 Data Transfer Instructions
• IN Accumulator, Port Address:
– It transfers the operand from specified port to accumulator
register.

– E.g.: IN AX, 0028 H

• OUT Port Address, Accumulator:

– It transfers the operand from accumulator to specified port.

– E.g.: OUT 0028 H, AX

 Data Transfer Instructions
• LEA Register, Src:
– It loads a 16-bit register with the offset
address of the data specified by the Src.
– E.g.: LEA BX, [DI]
• This instruction loads the contents of DI (offset)
into the BX register.
 Data Transfer Instructions
• LDS Des, Src:
– It loads 32-bit pointer from memory source to
destination register and DS.
– The offset is placed in the destination register and the
segment is placed in DS.
– To use this instruction the word at the lower memory
address must contain the offset and the word at the
higher address must contain the segment.
– E.g.: LDS BX, [0301 H]
 Data Transfer Instructions
• LES Des, Src:
– It loads 32-bit pointer from memory source to
destination register and ES.
– The offset is placed in the destination register and
the segment is placed in ES.
– This instruction is very similar to LDS except that it
initializes ES instead of DS.
– E.g.: LES BX, [0301 H]
 Data Transfer Instructions
• LAHF:
– It copies the lower byte of flag register to AH.

• SAHF:
– It copies the contents of AH to lower byte of flag register.

• PUSHF:
– Pushes flag register to top of stack.

• POPF:
– Pops the stack top to flag register.
 Arithmetic Instructions
• ADD Des, Src:
– It adds a byte to byte or a word to word.
– It effects AF, CF, OF, PF, SF, ZF flags.
– E.g.:
• ADD AL, 74H
• ADD DX, AX
• ADD AX, [BX]
 Arithmetic Instructions
• ADC Des, Src:
– It adds the two operands with CF.
– It effects AF, CF, OF, PF, SF, ZF flags.
– E.g.:
• ADC AL, 74H
• ADC DX, AX
• ADC AX, [BX]
 Arithmetic Instructions
• SUB Des, Src:
– It subtracts a byte from byte or a word from word.
– It effects AF, CF, OF, PF, SF, ZF flags.
– For subtraction, CF acts as borrow flag.
– E.g.:
• SUB AL, 74H
• SUB DX, AX
• SUB AX, [BX]
 Arithmetic Instructions
• SBB Des, Src:
– It subtracts the two operands and also the borrow
from the result.
– It effects AF, CF, OF, PF, SF, ZF flags.
– E.g.:
• SBB AL, 74H
• SBB DX, AX
• SBB AX, [BX]
 Arithmetic Instructions
• INC Src:
– It increments the byte or word by one.
– The operand can be a register or memory
location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– E.g.: INC AX
 Arithmetic Instructions
• DEC Src:
– It decrements the byte or word by one.
– The operand can be a register or memory
location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– E.g.: DEC AX
 Arithmetic Instructions
• AAA (ASCII Adjust after Addition):
– The data entered from the terminal is in ASCII format.
– In ASCII, 0 – 9 are represented by 30H – 39H.
– This instruction allows us to add the ASCII codes.
– This instruction does not have any operand.
• Other ASCII Instructions:
– AAS (ASCII Adjust after Subtraction)
– AAM (ASCII Adjust after Multiplication)
– AAD (ASCII Adjust Before Division)
 Arithmetic Instructions
• DAA (Decimal Adjust after Addition)
– It is used to make sure that the result of adding two
BCD numbers is adjusted to be a correct BCD number.
– It only works on AL register.
• DAS (Decimal Adjust after Subtraction)
– It is used to make sure that the result of subtracting
two BCD numbers is adjusted to be a correct BCD
number.
– It only works on AL register.
 Arithmetic Instructions
• NEG Src:
– It creates 2’s complement of a given
number.
– That means, it changes the sign of a
number.
 Arithmetic Instructions
• CMP Des, Src:
– It compares two specified bytes or words.
– The Src and Des can be a constant, register or memory
location.
– Both operands cannot be a memory location at the
same time.
– The comparison is done simply by internally
subtracting the source from destination.
– The value of source and destination does not change,
but the flags are modified to indicate the result.
 Arithmetic Instructions
• MUL Src:
– It is an unsigned multiplication instruction.
– It multiplies two bytes to produce a word or two words to
produce a double word.
– AX = AL * Src
– DX : AX = AX * Src
– This instruction assumes one of the operand in AL or AX.
– Src can be a register or memory location.
• IMUL Src:
– It is a signed multiplication instruction.
 Arithmetic Instructions
• DIV Src:
– It is an unsigned division instruction.
– It divides word by byte or double word by word.
– The operand is stored in AX, divisor is Src and the
result is stored as:
• AH = remainder AL = quotient

• IDIV Src:
– It is a signed division instruction.
 Arithmetic Instructions
• CBW (Convert Byte to Word):
– This instruction converts byte in AL to word in AX.
– The conversion is done by extending the sign bit of AL
throughout AH.
• CWD (Convert Word to Double Word):
– This instruction converts word in AX to double word in
DX : AX.
– The conversion is done by extending the sign bit of AX
throughout DX.
 Bit Manipulation Instructions
• These instructions are used at the bit level.
• These instructions can be used for:
– Testing a zero bit
– Set or reset a bit
– Shift bits across registers
 Bit Manipulation Instructions
• NOT Src:
– It complements each bit of Src to produce 1’s
complement of the specified operand.
– The operand can be a register or memory
location.
 Bit Manipulation Instructions
• AND Des, Src:
– It performs AND operation of Des and Src.
– Src can be immediate number, register or memory
location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the
same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.
 Bit Manipulation Instructions
• OR Des, Src:
– It performs OR operation of Des and Src.
– Src can be immediate number, register or memory
location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the
same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.
 Bit Manipulation Instructions
• XOR Des, Src:
– It performs XOR operation of Des and Src.
– Src can be immediate number, register or memory
location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the
same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.
 Bit Manipulation Instructions
• SHL Des, Count:
– It shift bits of byte or word left, by count.
– It puts zero(s) in LSBs.
– MSB is shifted into carry flag.
– If the number of bits desired to be shifted is 1, then
the immediate number 1 can be written in Count.
– However, if the number of bits to be shifted is more
than 1, then the count is put in CL register.
 Bit Manipulation Instructions
• SHR Des, Count:
– It shift bits of byte or word right, by count.
– It puts zero(s) in MSBs.
– LSB is shifted into carry flag.
– If the number of bits desired to be shifted is 1, then
the immediate number 1 can be written in Count.
– However, if the number of bits to be shifted is more
than 1, then the count is put in CL register.
 Bit Manipulation Instructions
• ROL Des, Count:
– It rotates bits of byte or word left, by count.
– MSB is transferred to LSB and also to CF.
– If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
– However, if the number of bits to be shifted is
more than 1, then the count is put in CL register.
 Bit Manipulation Instructions
• ROR Des, Count:
– It rotates bits of byte or word right, by count.
– LSB is transferred to MSB and also to CF.
– If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
– However, if the number of bits to be shifted is
more than 1, then the count is put in CL register.
 Program Execution Transfer Instructions
• These instructions cause change in the
sequence of the execution of instruction.
• This change can be through a condition or
sometimes unconditional.
• The conditions are represented by flags.
 Program Execution Transfer Instructions
• CALL Des:
– This instruction is used to call a subroutine or function
or procedure.
– The address of next instruction after CALL is saved
onto stack.
• RET:
– It returns the control from procedure to calling
program.
– Every CALL instruction should have a RET.
 Program Execution Transfer Instructions
• JMP Des:
– This instruction is used for unconditional jump
from one place to another.

• Jxx Des (Conditional Jump):

– All the conditional jumps follow some conditional
statements or any instruction that affects the flag.
 Conditional Jump Table
Mnemonic Meaning Jump Condition
JA Jump if Above CF = 0 and ZF = 0
JAE Jump if Above or Equal CF = 0
JB Jump if Below CF = 1
JBE Jump if Below or Equal CF = 1 or ZF = 1
JC Jump if Carry CF = 1
JE Jump if Equal ZF = 1
JNC Jump if Not Carry CF = 0
JNE Jump if Not Equal ZF = 0
JNZ Jump if Not Zero ZF = 0
JPE Jump if Parity Even PF = 1
JPO Jump if Parity Odd PF = 0
JZ Jump if Zero ZF = 1
 Program Execution Transfer Instructions
• Loop Des:
– This is a looping instruction.
– The number of times looping is required is placed
in the CX register.
– With each iteration, the contents of CX are
decremented.
– ZF is checked whether to loop again or not.
 String Instructions
• String in assembly language is just a
sequentially stored bytes or words.
• There are very strong set of string instructions
in 8086.
• By using these string instructions, the size of
the program is considerably reduced.
 String Instructions
• CMPS Des, Src:
– It compares the string bytes or words.

• SCAS String:
– It scans a string.
– It compares the String with byte in AL or with
word in AX.
 String Instructions
• MOVS / MOVSB / MOVSW:
– It causes moving of byte or word from one string
to another.
– In this instruction, the source string is in Data
Segment and destination string is in Extra
Segment.
– SI and DI store the offset values for source and
destination index.
 String Instructions
• REP (Repeat):
– This is an instruction prefix.
– It causes the repetition of the instruction until CX
becomes zero.
– E.g.: REP MOVSB STR1, STR2
• It copies byte by byte contents.
• REP repeats the operation MOVSB until CX becomes
zero.
 String Instructions
 String is a collection of bytes, words, or long-words that can be up to 64KB
in length
 String instructions can have at most two operands. One is referred to as source
string and the other one is called destination string
— Source string must locate in Data Segment and SI register points to the current
element of the source string
— Destination string must locate in Extra Segment and DI register points to the current
element of the destination string
DS : SI ES : DI
0510:0000 53 S 02A8:2000 53 S
0510:0001 48 H 02A8:2001 48 H
0510:0002 4F O 02A8:2002 4F O
0510:0003 50 02A8:2003 50
P P
0510:0004 50 P 02A8:2004 50 P
0510:0005 45 E 02A8:2005 49 I
0510:0006 52 R 02A8:2006 4E N
Source String Destination String
 Repeat Prefix Instructions
 REP String Instruction
— The prefix instruction makes the microprocessor repeatedly execute the string instruction
until CX decrements to 0 (During the execution, CX is decreased by one when the string
instruction is executed one time).
— For Example:

MOV CX, 5
REP MOVSB
By the above two instructions, the microprocessor will execute MOVSB 5 times.

— Execution flow of REP MOVSB::

While (CX!=0) Check_CX: If CX!=0 Then

{ CX = CX –1;
CX = CX –1; OR MOVSB;
MOVSB; goto Check_CX;
} end if
 String Instructions
 MOVSB (MOVSW)
— Move byte (word) at memory location DS:SI to memory location ES:DI and
update SI and DI according to DF and the width of the data being transferred
— It does not modify flags
—Example:

DS : SI ES : DI
MOV AX, 0510H 0510:0000 53 S 0300:0100
MOV DS, AX 0510:0001 48 H
MOV SI, 0 4F
0510:0002 O
MOVAX, 0300H
0510:0003 50
MOV ES, AX P
MOV DI, 100H 0510:0004 50 P
CLD 0510:0005 45 E
MOV CX, 5 52
0510:0006 R
REP MOVSB
Source String Destination String
 String Instructions
 CMPSB (CMPSW)
— Compare bytes (words) at memory locations DS:SI and ES:DI;
update SI and DI according to DF and the width of the data being compared
— It modifies flags
—Example:

Assume: ES = 02A8H DS : SI
DI = 2000H ES : DI
0510:0000 53 S 53 S
DS = 0510H 02A8:2000
SI = 0000H 0510:0001 48 H 48 H
02A8:2001
0510:0002 4F O 4F O
02A8:2002
CLD 0510:0003 50
P 50
02A8:2003 P
MOV CX, 9 50 P P
0510:0004 02A8:2004 50
REPZ CMPSB 45
0510:0005 E 49 I
02A8:2005
0510:0006 52 R 4E N
02A8:2006
What’s the values of CX after
The execution? Source String Destination String
 String Instructions
 SCASB (SCASW)
SCASB compares the byte in AL with the byte
at [ES:DI] or [ES:EDI], and sets the flags accordingly. It
then increments or decrements (depending on the
direction flag: increments if the flag is clear, decrements
if it is set) DI (or EDI).
SCASW and SCASD work in the same way, but they
compare a word to AX or a doubleword to EAX instead of
a byte to AL, and increment or decrement the
addressing registers by 2 or 4 instead of 1.

 LODSB (LODSW)
— Load byte (word) at memory location DS:SI to AL (AX);
update SI according to DF and the width of the data being transferred
— It does not modify flags

 STOSB (STOSW)
— Store byte (word) at in AL (AX) to memory location ES:DI;
update DI according to DF and the width of the data being transferred
— It does not modify flags
 Processor Control Instructions
• These instructions control the processor itself.
• 8086 allows to control certain control flags
that:
– causes the processing in a certain direction
– processor synchronization if more than one
microprocessor attached.
 Processor Control Instructions
• STC:
– It sets the carry flag to 1.

• CLC:
– It clears the carry flag to 0.

• CMC:
– It complements the carry flag.
 Processor Control Instructions
• STD:
– It sets the direction flag to 1.
– If it is set, string bytes are accessed from higher
memory address to lower memory address.

• CLD:
– It clears the direction flag to 0.
– If it is reset, the string bytes are accessed from lower
memory address to higher memory address.
 Addressing Modes

Addressing Modes Examples

 Immediate addressing MOV AL, 12H
 Register addressing MOV AL, BL
 Direct addressing MOV [500H], AL
 Register Indirect addressing MOV DL, [SI]
 Based addressing MOV AX, [BX+4]
 Indexed addressing MOV [DI+8], BL
 Based indexed addressing MOV [BP+SI], AH
 Based indexed with displacement addressing MOV CL, [BX+DI+2]

Exceptions
 String addressing
 Port addressing (e.g. IN AL, 79H)
 Machine Cycles
• Also Bus Cycles

• Definition:
– One discrete information transfer on the buses.

• This includes the address, data, and control

information.

Engr 4862 Microprocessors

 Machine Cycles
• A machine (bus) cycle consists of at least four
clock cycles, called T states.
• A specific, defined action occurs during each T
state (labeled T1 – T4)
– T1: Address is output
– T2: Bus cycle type (Mem/IO, read/write)
– T3: Data is supplied
– T4: Data latched by CPU, control signals removed

Engr 4862 Microprocessors

 By memory o

By micropro

Engr 4862 Microprocessors

 T States
• Why are there T states?
– In the 8086/8088, the address and data lines are
multiplexed.
– The microprocessor needs time to change the
signals during each bus cycle.
– Memory devices need time to decipher the
address value and then read/write the data
(access time)

Engr 4862 Microprocessors

 Timing
• The period of one bus cycle is at least four
times a clock cycle
– 10-MHz 8086 CPU
– Each clock cycle has a period of 100ns
– Machine cycle period is 400ns

Engr 4862 Microprocessors

 Timing
400 ns

100 ns

Engr 4862 Microprocessors

 Timing
• Although the system clock has a constant
period, the bus cycle does not
– Slow devices (memory or I/O) must request extra
time.
– The microprocessor inserts extra wait states
between states T3 and T4
• The alternatives are to slow down the system
clock, or use faster devices

Engr 4862 Microprocessors

 Timing

Wait state inserted here

Engr 4862 Microprocessors

 Pin Diagram of 8086
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16 / S3
AD12 4 37 A17 / S4
AD11 5 A18 / S5
36
AD10
6 35 A19/S6
AD9
AD8 7 34 BHE / S7
AD7 8 8086 33 MN/MX
AD6 9 32
AD5 RD
10
CPU 31 RQ / GT0 ( HOLD)
AD4 11
AD3 30 RQ / GT1 ( HLDA)
12
AD2 29 LOCK (WR)
13 S2 (M / IO )
AD1 28
AD0 14 27 S1_ (DT / R)
NMI 15 26 S0 (DEN)
INTR 16 25 QS0 (ALE)
24 QS1 (INTA)
CLK 17
18 23 TEST
GND
19 22 READY
20 21 RESET

M. Krishna Kumar MM/M1/LU3/V1/2004 5

 Minimum Mode Interface ( cont..)
Vcc GND

INTR
A0-A15,A16/S3 – A19/S6
INTA
Interrupt Address / data bus
interface
TEST

D0 – D15
NMI
8086
RESET ALE
MPU
BHE / S7
M / IO Memory
DMA HOLD I/O controls
DT / R
interface
HLDA RD

WR

Vcc
DEN
Mode select
READY
MN / MX

CLK clock

M. Krishna Kumar
Minimum Mode 8086 MPU
Block Diagram of theMM/M1/LU3/V1/2004 20
Minimum Mode Interface:
When the Minimum mode operation is selected, the 8086 provides
all control signals needed to implement the memory and I/O
interface.
• The signal read RD and write WR indicates that a read
cycle or a write bus cycle is in progress. The 8086 switches
bus
WR to logic 0 to signal external device that valid write or
output data are on the bus.
• On the other hand, RD indicates that the 8086 is
performing a read of data of the bus. During read
operations, one other control signal is also supplied. This
is
DEN ( data enable) and it signals external devices when
• they should put data on the bus.
There is one other control signal that is involved with
the memory and I/O interface. This is the READY
signal.
M. Krishna Kumar MM/M1/LU3/V1/2004 26
 ALE
Pin 25 (Output)

• This is an Address Latch Enable

signal.
• It indicates that valid address is
available on bus AD0 – AD15.
• It is an active high signal and
remains high during T1 state.
• It is connected to enable pin of
latch 8282.
 DEN
Pin 26 (Output)

• This is a Data Enable signal.

• This signal is used to enable
the transceiver 8286.
• Transceiver is used to
separate the data from the
address/data bus.
• It is an active low signal.
 DT / R
Pin 27 (Output)

• This is a Data Transmit/Receive

signal.
• It decides the direction of data
flow through the transceiver.
• When it is high, data is
transmitted out.
• When it is low, data is received
in.
ALE (Address latch enable)
When 1, address data bus contains a memory or I/O address.
DT/R (Data Transmit/Receive)
Data bus is transmitting/receiving data.
DEN (Data bus Enable)
Activates external data bus buffers.
BHE
Bus High Enable. Enables the most significant data bus bits
(D 15 -D 8 ) during a read or write operation. BHE is used to
enable the high order bus so as to differentiate between a word
operation and a byte operation.
 Minimum Mode 8086 System (cont..)
M / IO RD WR Transfer Type

0 0 1 I / O read
1 0 I/O write
0
1 0 1 Memory read
1 1 0 Memory write

Data Transfer table

M. Krishna Kumar MM/M1/LU3/V1/2004 49

 Minimum Mode 8086 System (cont..)
Clk
T1 T2 T3 TW T4
ALE

BHE S7 – S3
ADD / STATUS A19 – A16
Bus reserved
ADD / DATA A15 – A0 for data in D15 – D0

RD

DEN

DT / R

Read Cycle Timing Diagram for Minimum Mode

M. Krishna Kumar MM/M1/LU3/V1/2004 50
 Minimum Mode 8086 System (cont..)
T1 T2 T3 TW T4 T1

Clk

ALE

BHE S7 – S3
ADD / STATUS A19 – A16

ADD / DATA A15 – A0 Valid data D15 – D0

WR

DEN

DT / R

Write Cycle Timing Diagram for Minimum Mode

M. Krishna Kumar MM/M1/LU3/V1/2004 51
 Maximum Mode Interface
When the 8086 is set for the maximum-mode
configuration, it provides signals for implementing
multiprocessor / coprocessor system environment.

• By multiprocessor environment we mean that more

than one microprocessor exists in the system and
that each processor is executing its own program.
•
Usually in this type of system environment, there are
• some system resources that are common to all
processors.
• They are called as global resources. There are also other
resources that are assigned to specific processors. These
are known as local or private resources.

M. Krishna Kumar MM/M1/LU3/V1/2004 31

 Maximum Mode Interface (cont..)

• Coprocessor also means that there is a second processor in

the system. In this two processor does not access the bus
at the same time.
• One passes the control of the system bus to the other and
then may suspend its operation.
• In the maximum-mode 8086 system, facilities are
provided for implementing allocation of global resources
and passing bus control to other microprocessor or
coprocessor by The Intel 8289 is a Bus arbiter.

M. Krishna Kumar MM/M1/LU3/V1/2004 32

 INIT
S0 Multi Bus
BUSY
S1
CBRQ
S2 8289 Bus
LOCK BPRO
arbiter
BPRN
CRQLCK
RESB BREQ
CLK SYSB/RESB
Vcc GND
CLK AEN IOB BCLK
ANYREQ
INTR LOCK CLK AEN IOB
S0 MRDC
TEST CLK AEN IOB MWTC
S1 S0
NMI AMWC
S2 S1 8288 Bus IORC
RESET S2 controller IOWC
DEN AIOWC
DT/ R INTA
8086 MPU MCE / PDEN
ALE
DEN
DT / R
ALE
A0-A15,
A16/S3-A19/S6
MN/MX
D0 – D15
BHE
RD
READY
QS1, QS0
Local bus control
RQ / GT1 RQ / GT0 8086 Maximum mode Block Diagram
M. Krishna Kumar MM/M1/LU3/V1/2004 33
 The 8288 Bus Controller
• Provides the signals eliminated from the
8086/8088 by the maximum mode operation.

Figure 9–21 The 8288 bus controller; (a) block diagram and (b) pin-out.
 8288 Bus Controller Pin Functions
S2, S1, and S0
• Status inputs are connected to the status output
pins on 8086/8088.
– three signals decoded to generate timing signals

CLK
• The clock input provides internal timing.
– must be connected to the CLK output pin of
the 8284A clock generator
 8288 Bus Controller Pin Functions
ALE
• The address latch enable output is used to
demultiplex the address/data bus.
DEN
• The data bus enable pin controls the bidirectional
data bus buffers in the system.
DT/R
• Data transmit/receive signal output to control
direction of the bidirectional data bus buffers.
 8288 Bus Controller Pin Functions
AEN
• The address enable input causes the 8288 to
enable the memory control signals.
CEN
• The control enable input enables the command
output pins on the 8288.
IOB
• The I/O bus mode input selects either I/O
bus mode or system bus mode operation.
 8288 Bus Controller Pin Functions
AIOWC
• Advanced I/O write is a command output to an
advanced I/O write control signal.
IORC
• The I/O read command output provides
I/O with its read control signal.
IOWC
• The I/O write command output provides I/O with
its main write signal.
 8288 Pin Functions
AMWT
• Advanced memory write control pin provides
memory with an early/advanced write signal.
MWTC
• The memory write control pin provides memory
with its normal write control signal.
MRDC
• The memory read control pin provides memory
with a read control signal.
 8288 Bus Controller Pin Functions
INTA
• The interrupt acknowledge output acknowledges
an interrupt request input applied to the INTR pin.

MCE/PDEN
• The master cascade/peripheral data output
selects cascade operation for an interrupt
controller if IOB is grounded, and enables the I/O
bus transceivers if IOB is tied high.
 Maximum Mode Interface (cont..)
Status Inputs
CPU Cycles 8288
S2 S1 S0 Command
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOWC, AIOWC
0 1 1 Halt None
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC, AMWC
1 1 Passive None
1

Bus Status Codes

M. Krishna Kumar MM/M1/LU3/V1/2004 35

 Maximum Mode Interface (cont..)

• The 8288 produces one or two of these eight command

signals for each bus cycles. For instance, when the 8086
outputs the code S2S1S0 equals 001, it indicates that an I/O
read cycle is to be performed.
• In the code 111 is output by the 8086, it is signaling that no
bus activity is to take place.
• The control outputs produced by the 8288 are DEN,
DT/R
and ALE. These 3 signals provide the same functions as
those described for the minimum system mode. This set
of bus commands and control signals is compatible with
the Multibus and industry standard for interfacing
microprocessor systems.
M. Krishna Kumar MM/M1/LU3/V1/2004 36
 Maximum Mode 8086 System ( cont..)
One bus cycle
T1 T2 T3 T4 T1

Clk

AL
E
S2 – S0 Active Inactive Active

Add/Status BHE, A19 – A16 S7 – S3

Add/Data A15 – A0 D15 – D0

MRDC

DT / R

DEN

Memory Read Timing in Maximum Mode

M. Krishna Kumar MM/M1/LU3/V1/2004 63
 Maximum Mode 8086 System ( cont..)
One bus cycle
T1 T2 T3 T4 T1

Clk

ALE

S2 – S0 Active Inactive Active

ADD/STATUS BHE S7 – S3

ADD/DATA A15-A0 Data out D15 – D0

AMWC or
AIOWC
MWTC or IOWC

DT / R high
DEN

Memory Write Timing in Maximum mode.

M. Krishna Kumar MM/M1/LU3/V1/2004 64
 Maximum Mode 8086 System ( cont..)

Clk

RQ / GT

Another master CPU grant bus Master releases bus

request bus access

RQ/GT Timings in Maximum Mode.

M. Krishna Kumar MM/M1/LU3/V1/2004 65

THANKS
 Code Generation Flow
Assembly Code C Code

Assembler Compiler

Object Code Object Code

Linker

Machine Code
 Assembler Directives: Introduction

• Assembler directives give information to the assembler.

• They can be used to declare variables, create storage space

for results, to declare constants, and to label locations in the
code to be used as branch destinations.

• Most assemblers are ‘two-pass assemblers’.

– They read through the code once, looking for labels, and use them to
create the ‘symbol table’.
• The symbol table is a mapping between labels and values.
– On the second pass, they replace each occurrence of a label with its
value from the symbol table.

• Coding tip: Labels MUST be left justified, not indented. First

character must be a letter (not a number). Assembler only
looks at first 8 characters.
 Assembler Directives: Origin (ORG)

• Tells the assembler where to place your code

in memory.
• Operand given is the desired memory
location.
– ORG $001000 ; sets origin to be $001000

• Generally, we’ll put our code at $001000 and

our data (declared with DC, DS, etc) at
$002000.
 Assembler Directives: Declare Constant (DC)

• Declares a named variable in memory.

• The term ‘constant’ is misleading, because the
contents of that memory location can be changed.
• Use DC.B, DC.W, DC.L to declare different sizes of
variables.
• Operand given is initial value of variable.
– VAR DC.W $40 ; places $40 in memory location pointed
; to by VAR.

• Symbol table: the value of a label declared with DC is

the memory location of the label.
 Assembler Directives: Declare Storage (DS)

• Reserves space in memory for the result of a

future operation or future variables.
• Use DS.B, DS.W, DS.L to declare different sizes of
empty storage.

• Operand given is number of spaces to allocate,

where the size of a space is determined by the
extension (B,W,L)
– ARR DS.W 5 ; reserves 5 words in memory for ARR

• Symbol table: the value of a label declared with

DS is the memory location of the label.
 Assembler Directives: equal to (EQU)

• Declares a constant value.

• No need for extension here, assembler will treat the
number appropriately.

• Operand given is value to assign to label.

– CONST EQU 5 ; sets the value of CONST to 5
• Symbol table: the value of a label declared with EQU is
the value, NOT THE MEMORY LOCATION.

• EQU does not cause anything to be stored in memory.

 Assembler Directives: Code labels

• Labels an instruction in the program so that it can

be used as a branch target.

• All instructions are indented; a code label is

added by putting a left justified label on the same
line.
– LOOP ADD D1,D0 ; LOOP is the code label

• Symbol table: the value of a code label is the

memory location of the instruction on that line.
 Assembler Directives: end of code (END)

• Tells the assembler to stop looking for more

code.

• This should be the last line in any code file you

write.
 The Symbol Table
• Most assemblers are two-pass assemblers.
– On the first pass, any labels found in the program are put into the
symbol table along with the corresponding numerical value.
• Code labels – memory location of instruction
• Variable labels (DS, DC) – memory location of reserved memory
• Constants (EQU) – value of constant
– On the second pass, all labels in the code are replaced with their
values from the symbol table.

• Why use two passes?

– If the program contains a branch to a later location in the code (a
forward branch), the assembler won’t know where to find the branch
target because it would not have seen it yet.
Assembler Directives: An assembler directive is a message to
the assembler that tells the assembler something it needs to
know in order to carry out the assembly process; for example,
an assemble directive tells
the assembler where a program is to be located in memory.
We are going to use the following directives in this course:
Assume
• Used to tell the assembler the name of the logical segment it
should use for a specified segment.
• You must tell the assembler that what to assume for any
segment you use in the program.
• Example, ASSUME: CODE tells the assembler that the
instructions for the program are in segment named CODE.
DB – Defined Byte
• Used to declare a byte type variable or to set aside one or more
locations of type byte in memory.
• Example, PRICES DB 49H, 98H, 29H: Declare array of 3 bytes
named PRICES and initialize 3 bytes as shown.
 Assembler Directives(contd.)
DD – Define Double Word
• Used to declare a variable of type doubleword or to reserve a
memory location which can be accessed as doubleword.
DQ – Define Quadword
• Used to tell the assembler to declare the variable as 4 words of
storage in memory.
DT – Define Ten bytes
• Used to tell the assembler to declare the variable which is 10 bytes
in length or reserve 10 bytes of storage in memory.
DW – Define Word
• Used to tell the assembler to define a variable type as word or
reserve word in memory.
 Assembler Directives(contd.)
END – End the program
• To tell the assembler to stop fetching the instruction
and end the program execution.
• ENDP – it is used to end the procedure.
• ENDS – used to end the segment.
EQU – Equate
• Used to give name to some value or symbol.
EVEN – Align on Even memory address
• Tells the assembler to increment the location counter
to the next even address if it is not already at an even
address.
 Assembler Directives(contd.)
EXTRN
• Used to tell the assembler that the name or labels following
the directive are in some other assembly module.
GLOBAL – Declares symbols as PUBLIC or EXTRN
• Used to make the symbol available to other modules.
• It can be used in place of EXTRN or PUBLIC keyword.
GROUP – Group related segment
• Used to tell the assembler to group the logical segments
named after the directive into one logical segment.
• This allows the content of all the segments to be accessed
from the same group.
 Assembler Directives(contd.)
INCLUDE – include source code from file
• Used to tell the assembler to insert a block of source code
from the named file into the current source module. This
shortens the source code.
LABEL
• Used to give the name to the current value in the location
counter.
• The LABEL directive must be followed by a term which
specifies the type you want associated with that name.
LENGTH
• Used to determine the number of items in some data such
as string or array.
 Assembler Directives(contd.)
NAME
• Used to give a specific name to a module when the programs consisting of
several modules.
OFFSET
• It is an operator which tells the assembler to determine the offset or
displacement of named data item or procedure from the start of the
segment which contains it.
ORG – Originate
• Tells the assembler to set the location counter value.
• Example, ORG 7000H sets the location counter value to point to 7000H
location in memory.
• $ is often used to symbolically represent the value of the location counter.
It is used with ORG to tell the assembler to change the location according
to the current value in the location counter. E.g. ORG $+100.
 Assembler Directives(contd.)
PROC – Procedure
• Used to identify the start of the procedure.
PTR – Pointer
• Used to assign a specific type to a variable or a label.
• It is necessary to do this in any instruction where the
type of the operand is not clear.
Public
• It is used to tell the assembler that the specified label
or variable is accessible by other modules.
• This is useful in large programs which are generally
written in modules.
 Assembler Directives
SEGMENT
• Used to indicate that the start of a logical segment.
• Preceding the segment directive is the name you want to give to the
segment.
SHORT
• Used to tell the assembler that only a 1-byte displacement is needed to
code a jump instruction.
• If the jump destination is after the jump instruction in the program, the
assembler will automatically reserve 2 bytes for the displacement.
TYPE
• Tells the assembler to determine the type of a specified variable.
• The TYPE operator can be used in instruction such as ADD BX, TYPE
WORD_ARRAY, where we want to increment BX to point to the next word
in an array of words.
Data Transfer
Schemes
 Why do we need data transfer
schemes ?
• Availability of wide variety of I/O devices
because of variations in manufacturing
technologies e.g. electromechanical, electrical,
mechanical, electronic etc.

• Enormous variation in the range of speed.

• Wide variation in the format of data.

•
 Classification of Data Transfer
Schemes

Data transfer schemes

Programmed DMA
Data transfer Data transfer
Synchronous Asynchronous Interrupt Block Cycle stealing
mode mode Driven mode DMA mode DMA mode
 Programmed Data Transfer
Scheme
• The data transfer takes place under the control
of a program residing in the main memory.

• These programs are executed by the CPU

when an I/O device is ready to transfer data.

• To transfer one byte of data, it needs to

execute several instructions.

• This scheme is very slow and thus suitable

when small amount of data is to be transferred.
 Synchronous Mode of Data
Transfer
• Its used for I/O devices whose timing
characteristics are fast enough to be
compatible in speed with the communicating
MPU.

• In this case the status of the I/O device is not

checked before data transfer.

• The data transfer is executed using IN and

OUT instructions.
• Memory compatible with MPU are available.
Hence this method is invariably used with
compatible memory devices.

• The I/O devices compatible in speed with

MPU are usually not available. Hence this
technique is rarely used in practice
 Asynchronous Data Transfer
• This method of data transfer is also called
Handshaking mode.

• This scheme is used when speed of I/O device

does not match with that of MPU and the
timing characteristics are not predictable.

• The MPU fist sends a request to the device and

then keeps on checking its status.
• The data transfer instructions are executed
only when the I/O device is ready to accept or
supply data.

• Each data transfer is preceded by a requesting

signal sent by MPU and READY signal from
the device.
 Disadvantages
• A lot of MPU time is wasted during looping to
check the device status which may be
prohibitive in many situations.

• Some simple devices may not have status

signals. In such a case MPU goes on checking
whether data is available on the port or not.
Interrupt Driven Data Transfer
• In this scheme the MPU initiates an I/O device
to get ready and then it executes its main
program instead of remaining in the loop to
check the status of the device.

• When the device gets ready, it sends a signal

to the MPU through a special input line called
an interrupt line.

• The MPU answers the interrupt signal after

executing the current instruction.
• The MPU saves the contents of the PC on the
stack first and then takes up a subroutine called
ISS (Interrupt Service Subroutine).

• After returning from ISS the MPU again loads

the PC with the address that is just loaded in
the stack and thus returns to the main program.

• It is efficient because precious time of MPU is

not wasted while the I/O device gets ready.

• In this scheme the data transfer may also be

initiated by the I/O device.
 Multiple Interrupts
• The MPU has one interrupt level and several
I/O devices to be connected to it which are
attended in the order of priority.

• The MPU has several interrupt levels and one

I/O device is to be connected to each interrupt
level.
• The MPU has several interrupt levels and
more than one I/O devices are to be
connected to each interrupt level.

• The MPU executes multiple interrupts by

using a device polling technique to know
which device connected to which
interrupt level has interrupted
 Interrupts of 8085
On the basis of priority the interrupt signals are
as follows

• TRAP
• RST 7.5
• RST6.5
• RST5.5
• INTR

These interrupts are implemented by the

hardware
 Interrupt Instructions
• EI ( Enable Interrupt) This instruction sets the
interrupt enable Flip Flop to activate the interrupts.

• DI ( Disable Interrupt) This instruction resets the

interrupt enable Flip Flop and deactivates all the
interrupts except the non-maskable interrupt i.e.
TRAP

• RESET This also resets the interrupt enable Flip

Flop.
• SIM (Set Interrupt Mask) This enables\disables
interrupts according to the bit pattern in
accumulator obtained through masking.

• RIM (Read Interrupt Mask) This

instruction helps the programmer to know the
current status of pending interrupt.
 Call Locations and Hex – codes
for RST n
RST n Hex - code Call location
RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038
These instructions are implemented by the software
 DMA Data Transfer scheme
• Data transfer from I/O device to memory or
vice-versa is controlled by a DMA controller.
• This scheme is employed when large amount
of data is to be transferred.
• The DMA requests the control of buses
through the HOLD signal and the MPU
acknowledges the request through HLDA
signal and releases the control of buses to
DMA.
• It’s a faster scheme and hence used for high
speed printers.
 Block mode of data transfer
In this scheme the I/O device withdraws
the DMA request only after all the data
bytes have been transferred.

Cycle stealing technique

In this scheme the bytes are divided into
several parts and after transferring every part
the control of buses is given back to MPU and
later stolen back when MPU does not need it.
 Interrupts (cont..)
The processor has the following interrupts:
• INTR is a maskable hardware interrupt. The interrupt can
be enabled/disabled using STI/CLI instructions or using
more complicated method of updating the FLAGS
register
• with the help of the POPF instruction.
When an interrupt occurs, the processor stores FLAGS
register into stack, disables further interrupts, fetches
from the bus one byte representing interrupt type, and
jumps to interrupt processing routine address of which is
stored in location 4 * <interrupt type>. Interrupt
processing routine should return with the IRET
instruction.
M. Krishna Kumar MM/M1/LU3/V1/2004 83
 Interrupts (cont..)
• NMI is a non-maskable interrupt. Interrupt is processed
in
the same way as the INTR interrupt. Interrupt type of the
NMI is 2, i.e. the address of the NMI processing routine
is stored in location 0008h. This interrupt has higher
• priority
• then the maskable interrupt.
Software interrupts can be caused by:
• INT instruction - breakpoint interrupt. This is a type 3
interrupt.
• INT <interrupt number> instruction - any one
interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow
M. Krishna Kumar MM/M1/LU3/V1/2004 84
 Interrupts
• Single-step interrupt - generated if the TF flag is set.
This is a type 1 interrupt. When the CPU processes this
interrupt it clears TF flag before calling the interrupt
processing routine.
• Processor exceptions: Divide Error (Type 0), Unused
Opcode (type 6) and Escape opcode (type 7).
• Software interrupt processing is the same as for the
hardware interrupts.

M. Krishna Kumar MM/M1/LU3/V1/2004 85

THANKS