ASIC vs.

FPGA

Prof. S. S. S. P. Rao
Chief Technology Officer
Xilinx India Development Centre, Hyderabad

18th September 2006

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 Fundamental Law of
VLSI Technology …
“The number of transistors in an integrated circuit will double
every 18 months”

Today’s chips have close to 500 Million transistors !

Source: Intel web site
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 What is an ASIC?
What is an FPGA?

• ASIC (Application Specific Integrated Circuit)

 Fixed Function chip

• FPGA (Field Programmable Gate Array)

 Programmable chip

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 Processor vs. FPGA
Programming
• Processor: hardware • FPGA: hardware
functionality already functionality created by
exists, software ‘programming’
‘programs’ use of
hardware
PROGRAM INSTRUCTIONS PROGRAM GATES

MEM
A B

ALU

HW FIXED HW CREATED

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 Types of chips
Semi-conductors, ICs
• Available semiconductor chips can be
generalized to three types
1. Processor
2. Memory
Memory
3. Logic, Interface chips
- ASICs Processo
- FPGAs SOC r
• System on Chip (SOC) - Integrated
semiconductor chips containing all three
types Logic - I/F Chips
ASICs
FPGAs
Platform FPGAs can also implement SOC functions. Now have
2 PowerPCs, 10 Mb Memory and 11.1 Gbps IOs

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 Major Application Areas
Communication
- Wireless
- Wired
Radio tower
1 2
4 5
7 8
* 8
3
6
9
#
Automotive

Storage, Server
and Computing
FPGAs
ASICs
Disk array

Industrial
Examples:
Mars Rover
BMW Cars
SD

P ROLIANT
8000

Consumer
ESC

Electronics DLT
SD

Networking
Satellite dish
Satellite

Aerospace, Military, Mission Critical

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 FPGA and ASIC Market
FPGAs are taking market share away from ASICs
25 19.50% 20%

18%

20 16%
13.70%
14%
Billion $

15 12% ASIC
10% FPGA

10 8% FPGA %

6%

5 4%

2%

0 0%
2002 2003 2004 2005 2006 2007

• FPGA and ASIC combined market is still growing

Source: Gartner Dataquest (December 2003)
7
 ASIC, FPGA Design Starts
120,000 600

Density - Million Transistors/chip

102,000 500 M
FPGA, ASIC - Design Starts

100,000 500
FPGA
80,000 74,941 400

(-27%)
60,000 300

Density
40,000 200

20,000 100
8,950
ASIC 3,609
0 24 M (-60%) 0
1999 2000 2001 2002 2003 2004

Notes: 1. Decreasing number is due to increased integration (Moore’s law)

2. Designs of later years have much more equivalent functionality
Source: Gartner Dataquest (December 2003)
8
 FPGA Design Trend Relative to
ASICs Design Starts
500 500
Number of Designs (thousands)

400 400

300
100X
200

100
5 4
2 1.5
2001 2002 2003 2004
FPGA
Source: Gartner Group ASIC
9
 What’s Inside These Chips?
ASIC FPGA
Building block is
Building block is
Functionality a programmable
a ‘Cell’
(or Logic) unit called ‘LUT’
(Look Up Table)
Pre-defined
Routing is
routing tracks
custom-crafted
Interconnect which are
by hand or by
(or Routing) programmable
tool
(using a ‘switch’
matrix)
FPGA vs ASIC 10 Xilinx Copyright
 ASIC ‘Cell’
• Implements a fixed function like ‘And’, ‘XOR, ‘Mux’, ‘1 bit
adder’, etc (very much like TTL chips like the 74xx
series)
• The entire chip is then built ‘hierarchically’ with cells
being connected together to create more complex
functions (eg. Multipliers, decoders, etc)
‘Complex’ function Cells
A
B
Z
C
D

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 Types of ASICs
• Standard-cell based ASIC (80%):
– If ASIC is designed using a ‘standard’ library of cells, it is a
‘standard-cell’ or ‘cell-based’ ASIC
– Shorter design cycle, low-medium performance
• Custom ASIC (20%):
– If ASIC is designed using ‘custom’ and ‘semi-custom’ circuits, it
is a custom ASIC
– Longer design cycle, peak performance
‘Complex’ function
‘standard cell’ or
A ‘custom’ circuit
B
Z
C
D

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 ASIC: Major Components
• Typically, ASICs contain the following types of blocks:
– Clocking circuitry
– Datapath
– Control block
– Cache
– IO
– Specialized blocks based on application
– Routing

FPGA vs ASIC 13 Xilinx Copyright

FPGA Programming Technologies
SRAM Anti-fuse
Un-programmed Anti-fuse
SRAM A B Conductor
(open)
cell
A B

A B
Programmed Anti-fuse Insulator
A B (oxide)
(closed)

SRAM programmed with 1/0 to Anti-fuse programmed to

enable/disable connection enable connection between
between A and B A and B

FPGA vs ASIC 14 Xilinx Copyright

 SRAM vs. Anti-fuse

SRAM Anti-fuse
 Reprogrammable  One-Time Programmable
 Standard mfg process  Special mfg process
 Smaller size
 Larger size
 Faster
 Slower

Note: Majority of FPGAs in the industry are SRAM based

FPGA vs ASIC 15 Xilinx Copyright

 FPGA Look-Up Table (LUT)
• Combinatorial functions are implemented using a LUT
A B C D Z
• A 4-input LUT has 16 ‘programmable’ SRAM cells to
0 0 0 0 0
implement any arbitrary 4-input function
0 0 0 1 0
- 22**4 = 65,536!! Functions
0 0 1 0 0
• Each of the 16 SRAM cells is ‘programmed’ with the 0 0 1 1 1
output value of Z associated with that line in truth table
0 1 0 0 1
• Capacity limited by number of inputs, not complexity. 0 1 0 1 1
4 inputs has been found to be optimum . . .
Combinatorial Function
1 1 0 0 0
A
B 1 1 0 1 0
Z
C 1 1 1 0 0
D 1 1 1 1 1

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 LUT Implementation
A B C D Z
0 0 0 0 0
SRAM Cell
A B 0 0 0 1 0
CD
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
. . .
Z
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
16 SRAM cells in a LUT 1 1 1 1 1

FPGA vs ASIC 17 Xilinx Copyright

 Multiple Personalities
of a LUT
16 bit Shift Register • With minimal additional
16 x 1 RAM
circuitry, the same block
can serve multiple
4 input LUT purposes:
– 4 input LUT
– 16x1 RAM
– Shift Register

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 Simplified FPGA ‘Slice’
• Moving up in hierarchy,
an FPGA ‘slice’ has
Slice 0
– 2 LUTs for combinational
logic LUT Carry D
PRE
Q
CE
– 2 registers for sequential CLR

logic
– carry logic for fast adders
– 4 outputs, 2 registered + LUT Carry D PRE
CE Q

2 non-registered
CLR

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 Slices and CLB
• Each CLB (Configurable
Logic Block) contains 4 BUFT
COUT COUT

slices BUF T

Slice S3
• Local routing provides
feedback between slices in Slice S2
the same CLB, and it Switch
Matrix
SHIFT

provides routing to
Slice S1
neighboring CLBs
• A switch matrix provides Slice S0 Local Routing
access to general routing
resources CIN CIN

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 Interconnects Require
a Lot of Care !
• We tend to focus on functionality, but
watch out for those interconnects !!
With increased integration,
• Interconnects now contribute the

Local Interconnect
Switch
majority (70-80%) of the delay in Matrix
For
most chips (vs 20-30% for Global
Interconnect
functionality)
• Interconnects are the major source
of the most subtle, complex, difficult-
to-debug problems in a chip. Eg.
Clocking and Coupling problems, Functionality/L Interconnect/R
ogic outing
race conditions, etc

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 Today’s FPGA
2 PowerPC™
Processors 450
MHz

High-speed
11.1 Gbps
Serial
Transceivers

Programmable IO
+ DCI (Digitally
Controlled
Impedance)
18 Bit
36 Bit
18 Bit

VCCIO

>500 DSP Z
Z
datapaths Z Impedance
200, 000 LUTs 10Mbit Dual-
(~10 million
Control

Port™ RAM
gates)
FPGA vs ASIC 22 Xilinx Copyright
 VLSI Design Flow
Create Design
Plan & HDL/ HDL RTL
Budget Schematic Simulation
Integrate
IP Cores
Implement Synthesize
Functional to Create
Translate Simulation Netlist

Map Translate: Merge multiple design

Unique to
FPGA files into single netlist
Design- Map: Assign (‘map’) gates to
Place & Route
flow physical components (LUTs,
registers, etc) Create
Silicon:
Bit File
5 min (FPGA)
Attain (FPGA) vs.
Timing Timing Mask Files 5 months (ASIC)!
Simulation Closure (ASIC)

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 The Physical Silicon Chips
5 min vs. 5 months!
• FPGA
– implemented in physical silicon by using the ‘bit’ file.
– already manufactured. Hence the term ‘field’ programmable
• ASIC
– implemented in physical silicon by using the ‘masks’ (which
are expensive)
– transistors that implement the functionality/logic are
manufactured first (hence called ‘lower layers’) and then the
interconnect between them (hence called ‘upper layers’).
Metal
Oxide
Metal
Substrate
Diagram from: The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
FPGA vs ASIC 24 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx Copyright
 FPGA vs. ASIC
Design Methodology Comparison

FPGA ASIC
Asynchronous
Riskier to use because Lower risk since delays can
circuits
delays are hard to control be well controlled
Finite State One-hot encoding Gray, Binary, other encoding
Machines commonly used because of schemes
large number of registers
Deeper pipelines because of
As needed
Pipelining large number of registers
available
Scan, test Need to be added
Already in the chip
circuits separately

Takes 5 minutes!! Created Takes 5 months!! Created

Physical Silicon
using ‘bit’ files to program by manufacturing the chips
FPGA using ‘masks’

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 Key ‘Engineering’ Factors

• Cost
• Design cycle time / Time-To-Market
• Performance/Speed
• Density/Size
• Production volume
• Ease of fixing bugs, making changes
FPGA vs ASIC 26 Xilinx Copyright
 FPGA vs. ASIC Cost
High Design Cost of an ASIC is a major issue

• Total cost of IC product

= Design cost (also called NRE or Non-Recurring
Engineering cost) + Cost of parts sold
= Design cost + (# of parts sold * Cost/part)
• ASIC
– High design/NRE cost ($ 3 to 5 Million plus $ 0.5 to 1
Million for the masks plus prototype costs)
– Lower cost/part
• FPGA
– Low design/NRE cost
– Higher cost/part

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 FPGA vs. ASIC Cost
ASIC: High volumes needed to recover design cost

Total cost FPGA .09µ

FPGA .13µ
ASIC .09µ ASIC cost/part
ASIC Design is lower
Cost is much
higher ASIC .13µ
(and
increasing)!!

Volume
For each technology advance,
crossover volume moves higher
FPGA vs ASIC 28 Xilinx Copyright
 FPGA vs. ASIC Time-To-Market
FPGA Time-To-Market is 9 months vs 2-3 years for ASIC

ASIC
Spec Design & verification Silicon System Silicon First
Prototype Integration Production Ship

s s t ime
le
55%

FPGA
Spec Design & Verification System First
Integration Ship  FPGA flexibility allows late changes,
higher chance of meeting customer needs

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 Relative Cost of a Bug
Verify Verify Verify!!!

120
100
100

80

60

40 30

20 10
1 3
0
Arch Design Test System Customer

Note: Verification now takes longer than design!!

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 FPGA vs. ASIC Comparison
Bug Fixes/Design Changes

• FPGA: relatively straight-forward. Reprogram the FPGA

• ASIC: changes much harder to implement. 2 types of fixes:
– metal-only. Fix to interconnect/‘upper layers’ only. Less expensive
– full-turn. Fix to ‘transistors’/‘lower layers’. Entire chip has to be
refabricated. Most expensive
• Due to the high cost of fabrication, every attempt is made to find a
metal-only fix

Metal
Oxide
Metal
Substrate
Diagram from: The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
FPGA vs ASIC 31 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx Copyright
 FPGA vs. ASIC
Engineering Comparison
FPGA ASIC
Design Time /  
Time-To-Market ~ 9 Months (2-3 Years)

Design Cost  ($ 3-5 M, $1M
masks)
Performance
(speed, density, power)
 
Size (area)  
Total Cost  
at low-medium
at high volume
volume
Changes to design
 
FPGA vs ASIC 32 Xilinx Copyright
 FPGA & ASIC
Trends

• Due to Moore’s law, both FPGAs and ASICs are

increasingly target ‘System On Chip’ applications
• FPGAs:
– Glue logic ASIC bug fixes  ASIC prototypes 
ASIC replacement  System On Chip
• Due to increased integration, many ASIC market
requirements now met by FPGAs
– e.g. Virtex 4 has 2 processors, 10 Mb memory, 11.1
Gbps IO

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 Summary
• FPGAs and ASICs are 2 different approaches to a problem

• Driven by Moore’s law, low design cost and shorter design cycle time,
FPGAs are becoming an increasing % of solution!

• ASICs remain solution of choice only for high performance at

increasingly high volume needs – a decreasing % of solution!

• FPGAs (or programmable logic) is the fastest growing segment in the

semi-conductor industry!

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