ENCODERS/ DECODERS

MULTIPLEEXERS AND DEMULTIPLEXERS

Encoders:
An encoder is a digital function that produces a reverse
operation from that of a decoder. An encoder has 2n (or less)
input lines and n output lines. The output lines generate the
binary code for the 2n input variables. An example of an
encoder is shown following fig. The octal –to- binary encoder
consists of eight inputs, one for each of the eight digits, and
three outputs that generate the corresponding binary number.
It is constructed with OR gates whose inputs can be
determined from the truth table given in following. The low-
order output bit z is 1 if the input octal digit is odd. Output y
is 1 for octal digits 2, 3, 6, or 7. Output x is a 1 for octal digits
4, 5, 6, or 7. Note that D0 is not connected to any OR gate; the
binary output must be all 0’s. This discrepancy can be
resolved by providing one more output to indicate the fact that
all inputs are not 0’s.
 The encoder in following fig assumes that only one
input line can be equal to 1 at any time; otherwise the circuit
has no meaning. Note that the circuit has eight inputs and
could have 28 = 256 possible input combinations. Only eight
of three combinations have any meaning. The other input
combinations are don’t-care conditions.
Encoders of this type are not available in IC packages,
since they can be easily constructed with OR gates. The type
of encoder available in IC from is called a priority encoder.
These encoders establish an input priority to ensure that only
the highest-priority input line is encoded. Thus, in truth table,
if priority is given to an input with a higher subscript number
over one with a lower subscript number, then if both D2 and
D5 are logic-1 simultaneously, the output will be 101 because
D5 has a higher priority over D2.
Truth table of octal-to-binary encoder
D0 D1 D2 D3 D4 D5 D6 D7 x y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
 MULTIPLEXERS
1.A multiplexer is an MSI logic circuit
capable of selecting a single input bit from a
number of different sources and routing the
selected bit to a single output. The appropriate
input address lines determine the bit selected.
For instance, a multiplexer having three input
address lines (S, S, S0) is capable of selecting
one of eight possible input bits. There are
commercially available four-input, eight
input, and sixteen-input multiplexers.
 2.The 9312 is an eight-input multiplexer.
The active high select address appears at
(S2S,So) and E is an active low enable input.
The eight input bits appear at lo, I,, I, . . . I,,
and the selected bit appears un inverted at the
output Z. For instance, a select address of S2 =
1, S, = 0, and So = 1 will cause input bit I5 to
appear at Z (if I5 is high, Z is high; if I5 is low,
Z is low). The truth table in Fig. 10-30 shows
circuit operation. Note that when E is high the
circuit is disabled and the output Z goes low.
 (a) Logic Symbol (b) DIP

(c) Logic Diagram

 9312
Multiplexer

(d) Truth Table

Demultiplexer
18.The 74S139 provides a convenient means for
demultiplex-ng data. Demultiplexing means routing data
from a single source to one of a number of possible
destinations. Figure 10-23 shows a 74S139 connected to
demultiplex a data word consisting of 2 bits, Xo' and X, The
data bits are applied at the enable inputs and they appear at
an output specified by the address inputs A, and Ao. For
instance, when both address inputs are low (Ao = A, = 0),
and output O' follows the state of the enable input, low
when ENABLE is low and high when ENABLE is high. All
unselected outputs remain high. A demultiplexer for use
with larger data words can be constructed by simply
connecting additional 74S139s in parallel.
74S139 DeMultiplexer (a) Logic Symbol (b) Truth Table
Multiplexes and demultiplexers find a wide variety of uses in
moving digital data from one format to another. In addition,
these units are capable of being used to generate logic
functions in place of ordinary AND, OR, and NOT gates.