EDA Introduction: Professor: Sci.D., Professor Vazgen Melikyan

EDA Introduction
Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

Copyright © 2017 Synopsys, Inc. All rights reserved.
EDA Introduction
Lecture - 6
Developed By: Vazgen Melikyan
1
Course Overview
 Introduction
 1 lecture
 IC Design Data Formats and Tools
 4 lectures
 Electronic Design Methodology
 4 lectures
 IC Synthesis
 2 lectures
 Databases for EDA
 3 lectures
 IC Design Approaches and Flows
 3 lectures
 EDA Tools
 3 lectures
 Overview of Synopsys EDA Tools
 3 lectures

EDA Introduction
Lecture - 6
2
IC Design Approaches and
Flows

EDA Introduction
Lecture - 6
3
IC Design Levels
 Levels of abstraction: System
 System Level Design

Module
 Architecture / Algorithm Level Design
 Digital System Level Design
Gate
 Logical Level Design
 Electrical Level Design
Circuit
 Layout Level Design
 Semiconductor Level Design (more …)
Device
 EDA tools are used to help these and
Interconnect
n+ p n+
transformations.
 Technology advances give rise to new problems
EDA Introduction
Lecture - 6
4
Abstraction Levels in IC Design
Idea for New IC

CAD/Subproblem Level
Generic EDA Tools
Architectural Design Logic Design Physical Design

Behavioral/Architectural Level Register Transfer/Logic Level Cell/Mask Level
Behavioral Level and Logic Minimization and Layout Editing, Partitioning
Simulation Tools Simulation Tools Placement and Routing Tools

EDA Introduction
Lecture - 6
5
Architectural Design
 Carried out by experts Architectural Design

Behavioral/
 Decisions affect cost and Architectural Level
Behavioral Level and
performance Simulation Tools
 e.g. Architectural design of
microprocessor
 EDA programs aid
system architect
 Once architecture
defined, 2 tasks

EDA Introduction
Lecture - 6
6
Logic Design
 Data and control paths

Logic Design
contain logic blocks such Register Transfer/Logic Level
Logic Minimization and
as shift registers, Simulation Tools
multiplexors, buffers, ALU
 Implemented as PCB, IC
 In either case,
components placed on
layout surface and wired
together

EDA Introduction
Lecture - 6
7
Physical Design
 Refers to all synthesis steps which succeed

logic design but precede fabrication. Physical Design
 e.g. partitioning, placement, routing. Cell/Mask Level
Layout Editing, Partitioning
 Physical layout is crucial in determining Placement and Routing Tools
circuit performance, area, catastrophic yield,
reliability.
 Circuit performance: timing delays, crosstalk
metal, poly interconnect have finite
impedance. Long lines have large
impedance, longer delays, crosstalk.
Contacts, vias slow signals down.
 Area: functional and wiring affect yield
(number of defect free chips)
 Large chip area = low catastrophic yield

EDA Introduction
Lecture - 6
8
Design Options
Design Options
Custom Semicustom
Cell-based Array-based
Standard cells Pre-diffused Pre-wired

Compiled cells Macro cells (gate arrays) (FPGA's)

EDA Introduction
Lecture - 6
9
Full Custom Design Cycle
Structural/RTL Description
Ctrl
Memory Register Component

File Unit Component Design
Place and Route

PLA
comp I/O
RAM
... A/D

EDA Introduction
Lecture - 6
10
Full Custom Layout
Pad Metal1 Via Metal2
 Full control to the artwork designer in
placing and interconnecting circuit
blocks
 An expert can achieve high degree of Data
optimization in area and circuit path
PLA I/O
performance
 Difficult and expensive - many person
months to layout IC - only used in
ROM/
mass production cases
RAM
 Requires powerful EDA tools - layout
editor with DRC, compaction,
extraction Random
A/D
 Not for low production volume ASICs converter logic
 Standard layout architectures to cut
design time

EDA Introduction
Lecture - 6
11
Semi Custom Design Cycle
Structural/ HDL Programming
RTL Description
P_Inp: process (Reset, Clock)
Ctrl begin
if (Reset = '1') then
sum <= ( others => '0'
);
input_nums_read <= '0';
Mem Reg Comp. sum_ready <= '0';
File Unit
add82 : kadd8 port map (
a => add_i1, b => add_i2,
ci => carry, s => sum_o);
Mult_i1 <= sum_o(7 downto 0);
D C C B
A C C
D C D B Cell library
A B
C C C B
C D

EDA Introduction
Lecture - 6
12
Cell Based Design Cycle
Standard Macros O/I cell

cell
Design library
IP
Floorplanning
IP
IP
Routing Placement

EDA Introduction
Lecture - 6
13
Cell Based Design
process begin
Process wait until not
Design CLOCK'stable
and CLOCK=1; RTL / Logic
if(ENABLE='1') then
Rules TOGGLE<= not
TOGGLE;
end if;
end process;
Cell Library
EDA Tools
Design

EDA Introduction
Lecture - 6
14
Standard Cell Layout
 Standard cell - logic block performing specific

function
 e.g. NAND, XOR, NOR, D flip-flop
 Cell library - data on standard cells (function,

pin structure, layout in given technology)
 Cells have the same height
 Develop a floorplan for layout

 Select library cells, place in Si, interconnect
 Place and route simplified by dividing layout
into rows separated by horizontal routing
channels
 Very flexible gate array, wiring space not pre-
assigned, cell size can vary
 Fabrication more complex than gate array

EDA Introduction
Lecture - 6
15
Design Flow of Digital Standard Cell
Libraries
Databook Creation
is Required Specificatio
n Review
Databook
Generation Databook
MS Word; PDF;
Creation
is Not Required
Circuits Design
Simulation Results Do
Not
Schematic or Layout
comply Databook
Simulation Correction Required
results review
Simulations Results
comply Databook
Physical Layout
DRC, ERC, LVS Library Characterization

Errors reported No errors
reported
RC Parasitic
Characterization Results
Simulations Extraction Comply to Data
Results in Databook no
comply to Data
in Databook
Simulations
yes
Extracted Netlist Simulation Results Library Final Database Creation
with RCL Parasitics comply to Data
in Databook Deliverable views/files

EDA Introduction
Lecture - 6
16
Characterization Flow of Digital
Standard Cells
Input Data
Circuit RC
extracted netlists
Functional files
Timing
Characterization
Transition delay setup hold
recovery removal times
Power
Characterization
Internal power
leakager power
Model Building
(*.LIB,*.V,*.VHD,
*TLF,*.ALF)
Datasheet
Generation (*HTML)

EDA Introduction
Lecture - 6
17
Gate Array Layout
 Mask programmable gate array or field

programmable
 2/3D array of unconnected transistors
 Connections placed by either masking
(MPGA) or applied voltage (FPGA)
 2 types of personalization: intra-cell or inter-
cell
 Cell library maintained, intercell wiring by
layout software
 After personalization, wafer diced, chips
packaged
 Foundries stock large numbers of pre-
fabrication wafers
 Quick to fabricate
 Few processing steps, high catastrophic
yield, cheap

EDA Introduction
Lecture - 6
18
FPGAs
 Array of cells:
 Each cell performs a logic function
 Personalization:
 Soft: memory cell (e.g. Synopsys
HASP)
 Hard: anti-fuse (e.g. Actel)
 Immediate turn-around (for
low volumes)
 Inferior performances and
density
 Good for prototyping and re-
customization

EDA Introduction
Lecture - 6
19
Physical Design Cycle
The list of circuits turns to geometrical description called layout

 Refers to all synthesis steps which succeed logic design but precede fabrication, e.g.
partitioning, placement, routing.
 Physical layout crucial in determining circuit performance, area, yield, reliability.
1.Circuit Performance: timing, delays, crosstalk.
Metal, poly interconnect have finite impedance. Long lines have large impedance,
longer delays, crosstalk. Contacts, vias slow signals down.
2.Area: functional and wiring
affects yield (number of defect free chips)
large chip area = low catastrophic yield.

EDA Introduction
Lecture - 6
20
Physical Design Cycle (2)
Circuit design Fabrication
Compaction
Partitioning
Floorplanning and Placement

Routing

EDA Introduction
Lecture - 6
21
Simplified Cycle of Physical IC
Design
Circuit design
Physical design
Partitioning
Floorplanning and Placement
Routing
Compaction
No
Extraction and verification
Yes
Fabrication

EDA Introduction
Lecture - 6
22
Physical Design Strategies
3 main approaches differing in 2 ways

1. Layout surface
2.Structural constraints imposed on layout elements
FPGA Standard Cell Design

Full Custom
Implement a circuit by placing
Implementation using
Layout editing to generate metal connections between
transistors prefabrication on predefined logic blocks or cells
physical description of a circuit wafer in 3D array stored in the library

EDA Introduction
Lecture - 6
23
Design Approaches
Semi-custom
Cell-based Array-based
Macro Cells Pre-diffused

Standard Cells Generators:
Gate arrays Pre-wired
Memory
Hierarchical PLA Sea of gates Anti-fuse based
cells Sparse Logic Compacted Memory-based
Gate Matrix arrays
Custom Cell-based Pre-diffused Pre-wired

Density Very High High High Medium
Performance Very High High High Medium
Flexibility Very High High Medium Low
Design time Very Long Short Short Very Short

Manufacturing
time Medium Medium Short Very Short
Cost (low
volume) Very High High High Low
Cost (high
volume) Low Low Low High

EDA Introduction
Lecture - 6
24
Digital EDA Tools
 Digital design leverages highly on automation

 Binary logic abstraction
 Similar constraints and goals for each circuit
DRC Logic Timing

LVS ERC Verification Verification
Gate-Level FU-Level
Schematic HDL Synthesis Synthesis
Time

EDA Introduction
Lecture - 6
25
Analog EDA Tools
 Analog circuits are mostly custom designed

 Wide range of functionalities
 Implicit goals and constraints
 Different checks and objective for each circuit
DRC LVS
Multi-Variable
Optimization
SPICE Schematic
Time

EDA Introduction
Lecture - 6
26
IC Design Flow. Participants
 Digital design engineers

 Test engineers
 Layout engineers
 EDA engineers
 Semiconductor manufacturers

EDA Introduction
Lecture - 6
27
Digital IC Simple Design Flow
 Formation of digital IC specification

 Circuit obtained by gate level
 Functional verification of a gate-level circuit
 Layout automatic generation
 Layout verification
 Test creation
 IC fabrication

EDA Introduction
Lecture - 6
28
Simplified Chip Design Flow
process begin
wait until not
CLOCK'stable Register
and CLOCK=1;
if(ENABLE='1') then
TOGGLE<= not
Transfer
TOGGLE;
end if; Language
end process;
Synthesis
Netlist
Floorplanning
Placed
Netlist
Place and Route

Layout
Test Courtesy of IBM Sign Off

Masks

EDA Introduction
Lecture - 6
29
Digital IC Simple Design Flow
1. Formation of digital IC specification

 Description of digital IC functionality
 With the help of Verilog or VHDL in the specification
 An example of specification line:
 If incoming_call AND line_is_available then RING;
 The specifications of contemporary digital IC can contain millions of

lines, can be created by a collective of numerous participants within
a few months
 There exist ready specification libraries (example: DesignWare
Library, (V)HDL Compiler)

EDA Introduction
Lecture - 6
30
Digital IC Simple Design Flow (2)
2. Circuit obtained by gate level

 Automatic synthesis is implemented with the help of VHDL or
Verilog specification (example: Design Compiler, DesignWare
Library)

EDA Introduction
Lecture - 6
31
3. Functional verification of a gate-level circuit

 Verifying functionality and timing through Simulation, Timing Analysis,
Testbench Generation (example: VCS-MX, PrimeTime, VERA)
 Optimization of Digital circuits (example: Design Compiler, Power Compiler,
IC Compiler / IC Compiler II)
 Formal Verification (example: Formality)
0 0
1 1
0 0
1 1
1 1

EDA Introduction
Lecture - 6
32
4. Layout automatic generation

 Place and Route (example: IC Compiler)

EDA Introduction
Lecture - 6
33
5. Layout verification
 Post layout verification through
simulation (example: VCS-MX,
NanoSim, HSPICE)
 Layout versus Schematic
(LVS) and Design Rule
Checks (DRC) verification
(example: StarRC, IC
Validator)

EDA Introduction
Lecture - 6
34
6. Test creation
 Test Synthesis and Automatic Test Program Generation (example:
DFT Compiler, TetraMAX)
applying signals measuring response
+ +
expected response checking against expectations

EDA Introduction
Lecture - 6
35
7. IC fabrication
 Automated creation of GDSII file (example: IC Compiler / IC Compiler II)

EDA Introduction
Lecture - 6
36
7. IC fabrication
 Image correction (example: Proteus, Progen, IC Workbench, CATS)
 Yield Management (example: Yield Explorer, Odyssey )

EDA Introduction
Lecture - 6
37
 An example of GDSII file

STRNAME EXAMPLE
BOUNDARY
LAYER 02000200 60000201 1C000300 02000600 ...........`.... 000000
1 01000E00 02000200 60002500 01000E00 .....%.`........ 000010

DATATYPE 42494C45 4C504D41 58450602 12002500 .%....EXAMPLELIB 000020
0 413E0503 14000300 02220600 59524152 RARY..".......>A 000030
XY 1C00545A 9BA02FB8 4439EFA7 C64B3789 .7K...9D./..ZT.. 00004
-10000
60000000 01000E00 02000200 60000205 ...`...........` 000050
10000
20000
10000
OR 58450606 0C001100 01000E00 02000200 ..............EX 000060
0100020D 06000008 04000045 4C504D41 AMPLE........... 000070
20000 0000F0D8 FFFF0310 2C000000 020E0600 .......,........ 000080
-10000 FFFF204E 00001027 0000204E 00001027 '...N ..'...N .. 000090
-10000 0000F0D8 FFFFF0D8 FFFFF0D8 FFFFF0D8 ................ 0000A0
-10000
00000004 04000007 04000011 04001027 '............... 0000B0
-10000
00000000 00000000 00000000 00000000 ................ 0000C0
10000
ENDEL
ENDSTR

EDA Introduction
Lecture - 6
38
IC Design Steps
High-level Functional
Specifications Description
Description
Behavioral Structural
VHDL, C VHDL

EDA Introduction
Lecture - 6
39
IC Design Steps (2)
High-level Functional
Specifications
Description Description
Placed Gate-level Logic

and Routed Design Description
Design
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))

EDA Introduction
Lecture - 6
40
IC Design Methods
Design Cost / Quality Number of

Methods Development Companies
Time involved
Full Custom
Standard Cell
Library Design
ASIC – Standard
Cell Design
RTL-Level Design

EDA Introduction
Lecture - 6
41
Optimization: Levels of Abstraction
 Algorithmic
 Encoding data, computation scheduling, balancing delays of
components, etc.
 Gate-level
Level of detail
Effectiveness
 Reduce fan-out, capacitance
 Gate duplication, buffer insertion
 Layout / Physical-Design
 Move cells/gates around to shorten wires on critical paths
 Abut rows to share power / ground lines

EDA Introduction
Lecture - 6
42
IC Design Flow.
Detailed Digital Design IC Flow
Design Implementation
Blah blah blah
yada yada
Blahblah
Blah blah blah blah
yada yada
yidie yadie Blahblah
blah blah
So on and Blah blah
so forth yada yada
on andyidie yadie
on Blah
Specification
So on and blah blah
so forth
Jibber jabber jibber
on andyidie
just jawing on yadie
So on and
Jibberyack
jabber so forth
jibber
System
Yackety on and on
just jawing
Technology
Ya'll com back
Jibberyack
jabber jibber
Yackety
Ya'll com just
backjawing
Yackety yack
Ya'll com back
Analysis Process
Select Scripts
Architecture
TestbenchBlah blah blah
Initial constraints
Blah blah blah
yada yada yada yada
Blahblah
Blah blah blah blah Blahblah
Blah blah blah blah
yada yada
yidie yadie yada yada
yidie yadie
Blah Blahblah
blah blah blah Blah Blahblah
blah blah blah
So on and so forth yada yada So on and so forth yada yada
on andyidie yadie
on Blah blah blah on andyidie yadie
on Blah blah blah
So on and
Jibber jabber jibberso forth So on and
Jibber jabber jibberso forth
on andyidie
on yadie on andyidie
on yadie
RTL
just jawing
So on and so forth just jawing
So on and so forth
Gates Models / IP
Jibberyack
Yackety jabber jibber Jibberyack
Yackety jabber jibber
just on and on
jawing just on and on
jawing
Ya'll com back
Jibber jabber jibber Ya'll com back
Yackety yack Yackety yack
Ya'll com just
backjawing Ya'll com just
backjawing
Yackety yack Yackety yack
Ya'll com back Ya'll com back
RTL Verification
Synthesis
Links-to-Layout
Verification Design Planning
Gate-level Design
ATPG netlist Constraints
Gate-level Design for Manufacturing

verification
Post-Route
Verification Place & Route
Blah blah blah
yada yada
Blahblah
Blah blah blah blah
yada yada
yidie yadie
Blah Blahblah
blah blah blah
So on and so forth
GDSII
yada yada
on andyidie yadie
on Blah blah blah
Physical Design
So on and so forth
Physical Data
on andyidie
just jawing on yadie
So on and
Jibberyack
jabber so forth
jibber
Yackety on and on
Ya'll comjust
backjawing
Jibberyack
Yackety jabber jibber
just jawing
Checks
Ya'll com back
Creation Yackety yack

Ya'll com back

EDA Introduction
Lecture - 6
43

EDA Introduction: Professor: Sci.D., Professor Vazgen Melikyan

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EDA Introduction

Professor: Sci.D., Professor

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 Levels of abstraction: System

 System Level Design

Idea for New IC

Architectural Design Logic Design Physical Design

Synopsys University Courseware

 Carried out by experts Architectural Design

Synopsys University Courseware

 Data and control paths

Synopsys University Courseware

 Refers to all synthesis steps which succeed

Synopsys University Courseware

Standard cells Pre-diffused Pre-wired

Synopsys University Courseware

Memory Register Component

Place and Route

Synopsys University Courseware

Synopsys University Courseware

Mem Reg Comp. sum_ready <= '0';

Synopsys University Courseware

Standard Macros O/I cell

Synopsys University Courseware

Synopsys University Courseware

 Standard cell - logic block performing specific

 Cell library - data on standard cells (function,

 Develop a floorplan for layout

Synopsys University Courseware

DRC, ERC, LVS Library Characterization

Synopsys University Courseware

Synopsys University Courseware

 Mask programmable gate array or field

Synopsys University Courseware

Synopsys University Courseware

The list of circuits turns to geometrical description called layout

Synopsys University Courseware

Floorplanning and Placement

Synopsys University Courseware

Floorplanning and Placement

Synopsys University Courseware

3 main approaches differing in 2 ways

FPGA Standard Cell Design

Synopsys University Courseware

Macro Cells Pre-diffused

Custom Cell-based Pre-diffused Pre-wired

Performance Very High High High Medium

Flexibility Very High High Medium Low

Design time Very Long Short Short Very Short

Synopsys University Courseware

 Digital design leverages highly on automation

DRC Logic Timing

Synopsys University Courseware

 Analog circuits are mostly custom designed

Synopsys University Courseware

 Digital design engineers

Synopsys University Courseware

 Formation of digital IC specification

Synopsys University Courseware

Place and Route

Test Courtesy of IBM Sign Off