CpE242

Computer Architecture and Engineering

Designing a Single Cycle Datapath

CPE 442 single-cycle datapath.1 Intro. To Computer Architecture

 Outline of Today’s Lecture

° Recap and Introduction

• Where are we with respect to the BIG picture? (10 minutes)

° The Steps of Designing a Processor (10 minutes)

° Datapath and timing for Reg-Reg Operations (15 minutes)

° Datapath for Logical Operations with Immediate (5 minutes)

° Datapath for Load and Store Operations (10 minutes)

° Datapath for Branch and Jump Operations (10 minutes)

CPE 442 single-cycle datapath.2 Intro. To Computer Architecture

 Course Overview

Computer Design

Instruction Set Deign Computer Hardware Design

° Machine Language
° Compiler View ° Machine Implementation
° "Computer Architecture" ° Logic Designer's View
° "Instruction Set Processor"
° "Processor Architecture"

"Building Architect" ° "Computer Organization”

“Construction Engineer”

CPE 442 single-cycle datapath.3 Intro. To Computer Architecture

 The Big Picture: Where are We Now?

° The Five Classic Components of a Computer

Processor
Input
Control
Memory

Datapath Output

° Today’s Topic: Datapath Design

CPE 442 single-cycle datapath.4 Intro. To Computer Architecture

 The Big Picture: The Performance Perspective

° Performance of a machine was determined by:

• Instruction count
• Clock cycle time
• Clock cycles per instruction

° Processor design (datapath and control) will determine:

• Clock cycle time
• Clock cycles per instruction

° In the next two lectures:

• Single cycle processor:
- Advantage: One clock cycle per instruction
- Disadvantage: long cycle time

CPE 442 single-cycle datapath.5 Intro. To Computer Architecture

Recall the MIPS Instruction Set Architecture

CPE 442 single-cycle datapath.6 Intro. To Computer Architecture

CPE 442 single-cycle datapath.7 Intro. To Computer Architecture
CPE 442 single-cycle datapath.8 Intro. To Computer Architecture
CPE 442 single-cycle datapath.9 Intro. To Computer Architecture
 The MIPS Instruction
Formats
° All MIPS instructions are 32 bits long. The three instruction formats:
31 26 21 16 11 6 0
• R-type op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
31 26 21 16 0
• I-type op rs rt immediate
6 bits 5 bits 5 bits 16 bits
• J-type 31 26 0
op target address
6 bits 26 bits

° The different fields are:

• op: operation of the instruction
• rs, rt, rd: the source and destination register specifiers
• shamt: shift amount
• funct: selects the variant of the operation in the “op” field
• address / immediate: address offset or immediate value
• target address: target address of the jump instruction
CPE 442 single-cycle datapath.10 Intro. To Computer Architecture
 The MIPS
Subset
31 26 21 16 11 6 0
° ADD and subtract op rs rt rd shamt funct
• add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• sub rd, rs, rt
31 26 21 16 0
° OR Immediate: op rs rt immediate
• ori rt, rs, imm16 6 bits 5 bits 5 bits 16 bits

° LOAD and STORE

• lw rt, rs, imm16
• sw rt, rs, imm16

° BRANCH:
• beq rs, rt, imm16

° JUMP: 31 26 0
op target address
• j target
6 bits 26 bits

CPE 442 single-cycle datapath.11 Intro. To Computer Architecture

 An Abstract View of the Implementation

Clk
PC
Instruction Fetch
Instruction Address

Ideal Instruction Operand Fetch

Instruction
Memory Rd Rs Rt Imm
5 5 5 16
Execute
Data
Rw Ra Rb 32 Address
32 32 Ideal
32 32-bit DataOut

ALU
Data
Registers Data In Memory
Clk

Clk
32

CPE 442 single-cycle datapath.12 Intro. To Computer Architecture

 Clocking
Methodology
Clk
Setup Hold Setup Hold
Don’t Care

. . . .
. . . .
. . . .

° All storage elements are clocked by the same clock edge

° Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew

CPE 442 single-cycle datapath.13 Intro. To Computer Architecture

 An Abstract View of the Critical Path
° Register file and ideal memory:
• The CLK input is a factor ONLY during write operation
• During read operation, behave as combinational logic:
- Address valid => Output valid after “access time.”
Clk Critical Path (Load Operation) =
PC PC’s Clk-to-Q +
Instruction Address Instruction Memory’s Access Time +
Register File’s Access Time +
ALU to Perform a 32-bit Add +
Ideal Instruction Data Memory Access Time +
Instruction Setup Time for Register File Write +
Memory Rd Rs Rt Imm
5 5 5 16 Clock Skew

Data
Rw Ra Rb 32 Address
32 32 Ideal
32 32-bit
ALU DataOut
Data
Registers Data In Memory
Clk

Clk
32
CPE 442 single-cycle datapath.14 Intro. To Computer Architecture
 Outline of Today’s Lecture

° Recap and Introduction (5 minutes)

• Where are we with respect to the BIG picture? (10 minutes)

° The Steps of Designing a Processor (10 minutes)

° Datapath and timing for Reg-Reg Operations (15 minutes)

° Datapath for Logical Operations with Immediate (5 minutes)

° Datapath for Load and Store Operations (10 minutes)

° Datapath for Branch and Jump Operations (10 minutes)

CPE 442 single-cycle datapath.15 Intro. To Computer Architecture

 The Steps of Designing a
Processor
0) Instruction Set Architecture =>
Register Transfer Language Program
•Convert each instruction to RTL statements

1)Register Transfer Language program => Datapath

Design
•Determine Datapath components
•Determine Datapath interconnects

2)Datapath components => Control signals

3)Control signals => Control logic => Control Unit Design

CPE 442 single-cycle datapath.16 Intro. To Computer Architecture

 Step: 0) Instruction Set Architecture =>
Register Transfer Language Program

Register Transfer Language-RTL:

The ADD Instruction
° add rd, rs, rt

• mem[PC] Fetch the instruction from

memory

• R[rd] <- R[rs] + R[rt] The ADD operation

• PC <- PC + 4 Calculate the next instruction’s

address

CPE 442 single-cycle datapath.17 Intro. To Computer Architecture

 RTL: The Load
Instruction

° lw rt, rs, imm16

• mem[PC] Fetch the instruction from

memory

• Addr <- R[rs] + SignExt(imm16)

Calculate the memory
address

• R[rt] <- Mem[Addr] Load the data into the

register

• PC <- PC + 4 Calculate the next instruction’s

address
CPE 442 single-cycle datapath.18 Intro. To Computer Architecture
Step 1) : RTL To Data Path Design – Data Path Components,
CarryIn Combinational Logic Elements
° Adder A
32

Adder
Sum
32
B Carry
32
° MUX
Select

A
32
MUX

Y
32
B
32

° ALU
OP
A
32
ALU

Result
32
B Zero
32
CPE 442 single-cycle datapath.19 Intro. To Computer Architecture
Step 1) : RTL To Data Path Design – Data Path Components,
Storage Elements: Register

° Register Write Enable

• Similar to the D Flip Flop except Data In Data Out

- N-bit input and output N N

- Write Enable input

• Write Enable: Clk

- 0: Data Out will not change

- 1: Data Out will become Data In

CPE 442 single-cycle datapath.20 Intro. To Computer Architecture

 Step 1) : RTL To Data Path Design – Data Path Components,
Storage Elements: Register File
RW RA RB
Write Enable 5 5
° Register File consists of 32 registers: 5

• Two 32-bit output busses: busA

busW 32 32-bit 32
busA and busB
32 Registers
• One 32-bit input bus: busW Clk busB
32
° Register is selected by:
• RA selects the register to put on busA
• RB selects the register to put on busB
• RW selects the register to be written
via busW when Write Enable is 1

° Clock input (CLK)

• The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic
block: RA or RB valid => busA or busB valid after “access
time.”
CPE 442 single-cycle datapath.21 Intro. To Computer Architecture
 Step 1) : RTL To Data Path Design – Data Path Components,
Storage Elements: Idealized Memory
Write Enable Address
° Memory (idealized)
• One input bus: Data In Data In DataOut
• One output bus: Data Out 32 32
Clk
° Memory word is selected by:
• Address selects the word to put on Data Out
• Write Enable = 1: address selects the memory
memory word to be written via the Data In bus

° Clock input (CLK)

• The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic
block:
- Address valid => Data Out valid after “access time.”

CPE 442 single-cycle datapath.22 Intro. To Computer Architecture

 Step 1) : RTL To Data Path Design – Data Path Components,
Overview of the Instruction Fetch Unit
° The common RTL operations
• Fetch the Instruction: mem[PC]
• Update the program counter:
- Sequential Code: PC <- PC + 4
- Branch and Jump PC <- “something else”

Clk PC

Next Address
Logic

Address
Instruction Word
Instruction
Memory 32

CPE 442 single-cycle datapath.23 Intro. To Computer Architecture

 Outline of Today’s Lecture

° Recap and Introduction

• Where are we with respect to the BIG picture? (10 minutes)

° The Steps of Designing a Processor (10 minutes)

° Datapath and timing for Reg-Reg Operations (5 minutes)

° Datapath for Logical Operations with Immediate (5 minutes)

° Datapath for Load and Store Operations (10 minutes)

° Datapath for Branch and Jump Operations (10 minutes)

CPE 442 single-cycle datapath.24 Intro. To Computer Architecture

 Step 1): RTL To Data-Path Design
Determine Data-path
interconnects
31 26 21 16 11 6 0
RTL: The
op
ADDrs Instruction
rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

° add rd, rs, rt

• mem[PC] Fetch the instruction from

memory

• R[rd] <- R[rs] + R[rt] The actual operation

• PC <- PC + 4 Calculate the next instruction’s

address
CPE 442 single-cycle datapath.25 Intro. To Computer Architecture
 RTL: The Subtract
Instruction
31 26 21 16 11 6 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

° sub rd, rs, rt

• mem[PC] Fetch the instruction from

memory

• R[rd] <- R[rs] - R[rt] The actual operation

• PC <- PC + 4 Calculate the next instruction’s

address

CPE 442 single-cycle datapath.26 Intro. To Computer Architecture

 RTL To Data Path Design – Data-path for Register-Register
Operations
° R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt
• Ra, Rb, and Rw comes from instruction’s rs, rt, and rd fields
• ALUctr and RegWr: control logic after decoding the instruction

31 26 21 16 11 6 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Rd Rs Rt
RegWr 5 ALUctr
5 5
busA
Rw Ra Rb
busW 32 32-bit 32 Result

ALU
32 Registers 32
Clk busB
32

CPE 442 single-cycle datapath.27 Intro. To Computer Architecture

 Register-Register Timing
Clk
Clk-to-Q
PC Old Value New Value
Instruction Memory Access Time
Rs, Rt, Rd, Old Value New Value
Op, Func
Delay through Control Logic
ALUctr Old Value New Value

RegWr Old Value New Value

Register File Access Time
busA, B Old Value New Value
ALU Delay
busW Old Value New Value

Rd Rs Rt
RegWr 5 5 ALUctr Register Write
5
Occurs Here
busA
Rw Ra Rb
busW 32 32-bit 32 Result

ALU
32 Registers 32
Clk busB
32
CPE 442 single-cycle datapath.28 Intro. To Computer Architecture
 Outline of Today’s Lecture

° Recap and Introduction

• Where are we with respect to the BIG picture? (50 minutes)

° The Steps of Designing a Processor (10 minutes)

° Datapath and timing for Reg-Reg Operations (15 minutes)

° Datapath for Logical Operations with Immediate (5 minutes)

° Datapath for Load and Store Operations (10 minutes)

° Datapath for Branch and Jump Operations (10 minutes)

CPE 442 single-cycle datapath.29 Intro. To Computer Architecture

 RTL: The OR Immediate
Instruction
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

° ori rt, rs, imm16

• mem[PC] Fetch the instruction from memory

• R[rt] <- R[rs] or ZeroExt(imm16)

The OR operation

• PC <- PC + 4 Calculate the next instruction’s address

31 16 15 0
0000000000000000 immediate
16 bits 16 bits

CPE 442 single-cycle datapath.30 Intro. To Computer Architecture

 Datapath for Logical Operations with
Immediate
° R[rt] <- R[rs] op ZeroExt[imm16]] Example: ori rt, rs, imm16

31 26 21 16 11 0
op rs rt immediate
6 bits 5 bits 5 bits rd 16 bits

Rd Rt
RegDst
Mux
Don’t Care
Rs (Rt) ALUctr
RegWr 5 5 5
busA
Rw Ra Rb
busW 32 Result
32 32-bit

ALU
32 Registers 32
Clk busB
32
Mux
ZeroExt

imm16
16 32
ALUSrc
CPE 442 single-cycle datapath.31 Intro. To Computer Architecture
 Outline of Today’s Lecture

° Recap and Introduction

• Where are we with respect to the BIG picture? (50 minutes)

° The Steps of Designing a Processor (10 minutes)

° Datapath and timing for Reg-Reg Operations (15 minutes)

° Datapath for Logical Operations with Immediate (5 minutes)

° Datapath for Load and Store Operations (10 minutes)

° Datapath for Branch and Jump Operations (10 minutes)

° Assignment #3

CPE 442 single-cycle datapath.32 Intro. To Computer Architecture

 RTL: The Load
Instruction 31 26 21 16 0
op rs rt immediate
° lw rt, rs, imm16 6 bits 5 bits 5 bits 16 bits

• mem[PC] Fetch the instruction from memory

• Addr <- R[rs] + SignExt(imm16)

Calculate the memory address
R[rt] <- Mem[Addr] Load the data into the register

• PC <- PC + 4 Calculate the next instruction’s address

31 16 15 0
0000000000000000 0 immediate
SignExt
16 bits 16 bits
operation 31 16 15 0
1111111111111111 1 immediate
16 bits 16 bits
CPE 442 single-cycle datapath.33 Intro. To Computer Architecture
 Datapath for Load
Operations
° R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
31 26 21 16 11 0
op rs rt immediate
6 bits 5 bits 5 bits rd 16 bits

Rd Rt
RegDst
Mux
Don’t Care
Rs (Rt) ALUctr
RegWr 5 5 5 MemtoReg
busA
Rw Ra Rb
busW 32
32 32-bit

ALU
32 Registers 32

Mux
Clk busB MemWr 32
32
Mux

WrEn Adr
Extender

Data In
imm16 32 Data
16 32 Memory
Clk
ALUSrc

CPE 442 single-cycle datapath.34 ExtOp Intro. To Computer Architecture

 RTL: The Store
Instruction
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

° sw rt, rs, imm16

• mem[PC]Fetch the instruction from memory

• Addr <- R[rs] + SignExt(imm16)

Calculate the memory address

• Mem[Addr] <- R[rt] Store the register into memory

• PC <- PC + 4 Calculate the next instruction’s address

CPE 442 single-cycle datapath.35 Intro. To Computer Architecture

 Datapath for Store
Operations
° Mem[R[rs] + SignExt[imm16] <- R[rt]] Example: sw rt, rs, imm16
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

Rd Rt
RegDst
Mux
Rs Rt ALUctr
RegWr 5 5 5 MemWr MemtoReg
busA
Rw Ra Rb
busW 32
32 32-bit

ALU
32 Registers 32

Mux
Clk busB 32
Mux

32
WrEn Adr
Extender

Data In 32
imm16 Data
32
16 Memory
ALUSrc Clk

CPE 442 single-cycle datapath.36 ExtOp Intro. To Computer Architecture

 Outline of Today’s Lecture

° Recap and Introduction

• Where are we with respect to the BIG picture? (10 minutes)

° The Steps of Designing a Processor (10 minutes)

° Datapath and timing for Reg-Reg Operations (15 minutes)

° Datapath for Logical Operations with Immediate (5 minutes)

° Datapath for Load and Store Operations (10 minutes)

° Datapath for Branch and Jump Operations (10 minutes)

CPE 442 single-cycle datapath.37 Intro. To Computer Architecture

 RTL: The Branch
Instruction
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

° beq rs, rt, imm16

• mem[PC] Fetch the instruction from

memory

• Cond <- R[rs] - R[rt] Calculate the branch

condition

• if (COND eq 0) Calculate the next

instruction’s address
PC <- PC + 4 + ( SignExt(imm16) x 4 )
else PC <- PC + 4 Intro. To Computer Architecture
CPE 442 single-cycle datapath.38
 Step 1) : RTL To Data Path Design – Data Path Components,
Overview of the Instruction Fetch Unit
° The common RTL operations
• Fetch the Instruction: mem[PC]
• Update the program counter:
- Sequential Code: PC <- PC + 4
- Branch and Jump PC <- “something else”

Clk PC

Next Address
Logic

Address
Instruction Word
Instruction
Memory 32

CPE 442 single-cycle datapath.39 Intro. To Computer Architecture

 Datapath for Branch
Operations
° beq rs, rt, imm16 We need to compare Rs and Rt!
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

Rd Rt Branch Clk
PC
RegDst
Mux
Rs Rt ALUctr imm16
RegWr 5 5 5 Next Address
busA 16 Logic
Rw Ra Rb
busW 32
32 32-bit

ALU
32 Registers
Clk busB Zero To Instruction
32 Memory
Mux
Extender

imm16 32
16
ALUSrc

CPE 442 single-cycle datapath.40 ExtOp Intro. To Computer Architecture

 Binary Arithmetics for the Next Address

° In theory, the PC is a 32-bit byte address into the instruction memory:

• Sequential operation: PC<31:0> = PC<31:0> + 4
• Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4

° The magic number “4” always comes up because:

• The 32-bit PC is a byte address
• And all our instructions are 4 bytes (32 bits) long

° In other words:
• The 2 LSBs of the 32-bit PC are always zeros
• There is no reason to have hardware to keep the 2 LSBs

° In practice, we can simply the hardware by using a 30-bit PC<31:2>:

• Sequential operation: PC<31:2> = PC<31:2> + 1
• Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16]
• In either case: Instruction Memory Address = PC<31:2> concat “00”

CPE 442 single-cycle datapath.41 Intro. To Computer Architecture

 Next Address Logic: Expensive and Fast Solution
° Using a 30-bit PC:
• Sequential operation: PC<31:2> = PC<31:2> + 1
• Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16]
• In either case: Instruction Memory Address = PC<31:2> concat “00”

30
Addr<31:2>
30 Addr<1:0>
PC

“00”
30 0
Adder

Instruction
30

Mux
Memory
“1”
Adder 1
32
Clk 30
SignExt

imm16 30
Instruction<15:0> 16 Instruction<31:0>

Branch Zero

CPE 442 single-cycle datapath.42 Intro. To Computer Architecture

 Next Address Logic: Cheap and Slow Solution
° Why is this slow?
• Cannot start the address add until Zero (output of ALU) is valid

° Does it matter that this is slow in the overall scheme of things?

• Probably not here. Critical path is the load operation.

30

Addr<31:2>
PC

30 “1” Addr<1:0>
“00”
“0” Carry In Instruction
0
Memory

Adder
Mux

Clk 30
SignExt

1 32
imm16 30 30
Instruction<15:0> 16
Instruction<31:0>

Branch Zero

CPE 442 single-cycle datapath.43 Intro. To Computer Architecture

 RTL: The Jump
Instruction
31 26 0
op target address
6 bits 26 bits

°j target

• mem[PC] Fetch the instruction from

memory

• PC<31:2> <- PC<31:28> concat target<25:0>

Calculate the next instruction’s address

CPE 442 single-cycle datapath.44 Intro. To Computer Architecture

 Instruction Fetch
Unit
°j target
• PC<31:2> <- PC<31:29> concat target<25:0>
30
Addr<31:2>
PC<31:28> 30
Addr<1:0>
4 “00”
Target 1 Instruction
Instruction<25:0> 30

Mux
26 Memory
PC

0
30 0 32
Adder

30

Mux
“1”
Adder

1 Jump Instruction<31:0>
Clk 30
SignExt

imm16 30
Instruction<15:0> 16

Branch Zero
equal
CPE 442 single-cycle datapath.45 Intro. To Computer Architecture
 Putting it All Together: A Single Cycle Datapath
° We have everything except control signals (underline)

Branch Instruction<31:0>
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Jump Fetch Unit
Rd Rt
RegDst Clk
1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr
busA Zero MemWr MemtoReg
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32
Mux

32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc

ExtOp
CPE 442 single-cycle datapath.46 Intro. To Computer Architecture