BY:-

K16ES07
TOPIC :- K16ES41 .
FABRICATION OF INTEGRATED CIRCUITE K16ES39 .
 Integrated circuit
A chip or microchip, is a semiconductor wafer
on which thousands or millions of tiny
resistors, capacitors, and transistors are
fabricated .
1) Wafer production

2) Masking
3) Etching
4) Doping
5) Metallization
1) Wafer production
 Wafer is round silica of semiconductor material such
as silicon

 First purified polycrystalline silicon is created from

the sand

 it is heated to produce molten liquid

 A small piece of solid silicon is dipped on the

molten liquid

 Solid silicon (seed) is slowly pulled from the melt

 Liquid cools to form single crystal ingot

2) Masking

 PHOTOLITHOGRAPHY is a technique that is used to transfer

The geometry patterns mask to wafer.
3) Etching
 Etching is used to remove material selectively in order
to create patterns.
 The unmasked material can be removed either by etching.
4) Doping
 To alter the electrical character of silicon, atom with one
less electron than silicon such as boron and atom with one
electron greater then silicon such as phosphorous are
Introduced into the area

 The P-type (boron) and N-type (phosphorous)

are created to reflect their conducting characteristics.

Ion Atomic diffusion

implantation
5) Metallization
 It is used to create contact with silicon and to make
interconnections on chip
 A thin layer of aluminum is deposited over the
whole wafer
P-WELL

A B C
 P-WELL

P-WELL

n+ P+ P+ n+ n+ P+

P-well
 P-WELL

Primarily, start the process with a N-substrate

 P-WELL

The oxidation process is done by using high-purity

oxygen and hydrogen. To form the layer of SiO2
 P-WELL

A light-sensitive polymer that softens whenever exposed to

light is called as Photoresist layer. It is formed.
 P-WELL

The photoresist is exposed to UV rays through

the P-well mask
 P-WELL

A part of the photoresist layer is removed by treating the

wafer with the basic or acidic solution.
 P-WELL

The SiO2 oxidation layer is removed through the open area

made by the removal of photoresist using hydrofluoric acid.
 P-WELL

The entire photoresist layer is stripped off

 P-WELL

using ion implantation or diffusion process P-well is

formed.

P-well
 P-WELL

Using the hydrofluoric acid, the remaining SiO2 is

removed.

P-well P-well
 P-WELL

Chemical Vapor Deposition (CVD) process is used to deposit a very thin

layer of gate oxide.

P-well P-well
 P-WELL

Except the two small regions required for forming the Gates of
NMOS and PMOS, the remaining layer is stripped off

P-well P-well
 P-WELL

an oxidation layer is formed on this layer with two small regions for
the formation of the gate terminals of NMOS and PMOS.

P-well
P-well
 P-WELL

By using the masking process small gaps are made for

the purpose of P-diffusion

P-well P-well
 P-WELL

The p-type (p+) dopants are diffused or ion implanted, and the three
p+ are formed for the formation of the terminals of PMOS.

P+ P+ P+

P-well P-well
 P-WELL

The remaining oxidation layer is stripped off

P+ P+
P+

P+ P+ P+
P-well P-well
 P-WELL

Similar to the above P-diffusion process, the N-diffusion regions

are diffused to form the terminals of the PMOS.

n+ P+ P+ n+ n+ P+

P+ P+ P+

P-well
P-well
 P-WELL

A thick-field oxide is formed in all regions except the

terminals of the PMOS and NMOS.

n+ P+ P+ n+ n+ P+
n+ P+ P+ n+ n+ P+

P-well P-well
 P-WELL

Aluminum is sputtered on the whole wafer.

n+ P+ P+ n+ n+ P+
n+ P+ P+ n+ n+ P+

P-well P-well
 P-WELL

The excess metal is removed from the wafer layer.

n+ P+ P+ n+ n+ P+

P-well P-well
 P-WELL

The terminals of the PMOS and NMOS are made from

respective gaps
P-mos
N-mos

n+ P+ P+ n+ n+ P+
n+ P+ P+ n+ n+ P+

P-well P-well
 P-WELL P-mos

 A PMOS transistor is made up of p-type source and

drain and a n-type substrate.

 A high voltage on the gate will cause a PMOS not to

conduct, while a low voltage on the gate will cause it to
conduct

 PMOS technology is low cost and has a good noise

immunity.
 P-WELL P-mos

 Take Pure Si single crystal

 P-WELL P-mos

 N-type impurity is lightly doped

-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

 SiO2 Deposited over si surface

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

Photoresist is deposited over SiO2 layer

Photoresist
Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

 Photoresist layer is exposed UV Light

to UV Light through a mask

Mask-1

Photoresist
Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

Developer
removes
unpolymerised Polymerised
photoresist. It will Photoresist

cause no effect on -------------------------------

Si surface ----------------------------------
Thick SiO2
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (1 µm)
----------------------------------
 P-WELL P-mos

 Etching [HF acid is used] will remove SiO2 layer which is in

direct contact with etching solution

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

 unpolymerised photoresist is also etched away [using H2SO4]

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

Polysilicon layer
(1 – 2 µm)
 A thin layer of polysilicon is grown over the entire chip
surface to form GATE

-------------------------------
---------------------------------- Thin SiO2
Thick SiO2 (0.1 µm)
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(1 µm)
----------------------------------
 P-WELL P-mos

Photoresist
 A layer of photoresist is grown over polysilicon layer

Polysilicon
layer

------------------------------- Thin SiO2

---------------------------------- (0.1 µm)
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2
---------------------------------- (1 µm)
 P-WELL P-mos

UV Light

 Photoresist is exposed to UV Light

Mask-2

-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
Mask-2 is used to deposit
Polysilicon to form gate.
 P-WELL P-mos

 Etching will remove that portion

of Thin SiO2 which is not exposed to
UV light Polysilicon
Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

 Polymerised photoresist is also stripped away Polysilicon used as GATE

(1 – 2 µm)

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
 P-WELL P-mos

GATE

 P+ Doping to form SOURCE and DRAIN SOURCE DRAIN

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------
----------------------------------
 P-WELL P-mos

 A thick layer of SiO2 (1 µm) is again grown.

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
 P-WELL P-mos

 Photoresist is grown over thick UV Light

SiO2. Selected areas of the poly GATE

and SOURCE and DRAIN are exposed Mask-3

where contact cuts are to be made Mask-3 is used to make contact cuts for S, D and G.
Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
 P-WELL P-mos

The region of photoresist which is not

exposed by UV light will become Mask-3

soft. This unpolymerised photoresist and

SiO2 below it are etched away. Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
 P-WELL P-mos

 The contact cuts are formed for S,

Mask-3
D and G (hardened photoresist is
stripped away).
Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
 P-WELL P-mos

 Metal (aluminium) is deposited over the surface of whole

chip (1 µm thickness).

Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
 P-WELL P-mos

Photoresist

 Photoresist is deposited over the metal.

Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
 P-WELL P-mos

UV Light

 UV Light is passed through Mask-4

(with a aim of removing all metal Mask-4

other than metal in contact-cuts).

Photoresist
Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
Mask-4 is used to deposit metal in contact cuts of S, D and G.
 P-WELL P-mos

 Photoresist and metal which is not exposed to UV

light are etched away Mask-4

Photoresist
Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2 Thick SiO2
(1 µm) (1 µm)
----------------------------------
 P-WELL P-mos

SOURCE DRAIN
GATE

 Final P-MOS Transistor

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
p p
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------
----------------------------------
P-WELL P-mos

P-mos
N-mos

n+ P+ P+ n+ n+ P+

P-well
 P-WELL P-mos

Step1:
N or p type substrate is taken Initially
Step2:
Epitaxial Layer Deposition, Lightly Doped Epitaxial
Layer is Deposited above n+ or p+ Substrate.
Step3:
Tub Formation
n -well-Formation
Protect certain region in this by using an oxide nitride mask
Phosphorus implantation
Form n-well
The oxide is going to be formed only over the n-well
 P-WELL P-mos

Step4:
p -well-Formation
Protect certain region in this by using an oxide nitride mask
Boron implantation
Form p-well
Entire substrate to an oxidation process
Implant The p-well
Step 5:
Polysilicon gates Are Formed for n-well and p-well by Using Photo-Etching
Process
Step 6:
n+ Diffusion is Formed in p-well
p+ Diffusion is Formed in n-well
Step 7:

Metalization Process (Metal Contacts Are Created)