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• DC Analysis
– DC value of a signal in static conditions
Vout
C
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Region nMOS pMOS Vin
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
Courtesy : Prof Andrew Mason
Noise Margin
• Input Low Voltage, VIL
– Vin such that Vin < VIL = logic 0
– point ‘a’ on the plot
• where slope, Vin 1
Vout
• Input High Voltage, VIH
– Vin such that Vin > VIH = logic 1
– point ‘b’ on the plot
• where slope =-1
• Voltage Noise Margins Error in Fig : Replace VOH to VOL
– measure of how stable inputs are with respect to signal interference
– VNMH = VOH - VIH = VDD - VIH
– VNML = VIL - VOL = VIL
– desire large VNMH and VNML for best noise immunity
n p n
(V Vtn ) VDD VM Vtp
2
(VM Vtn )2
2
(VDD VM Vtp )2 p M
– solve for VM n
VDD Vtp Vtn
p
VM
n
1
p