Combinational vs.

Sequential
Combinational Circuit
• always gives the same output for a given set of inputs
ex: adder always generates sum and carry,
regardless of previous inputs
Sequential Circuit
• stores information
• output depends on stored information (state) plus input
so a given input might produce different outputs,
depending on the stored information
• example: ticket counter
advances when you push the button
output depends on previous state
• useful for building “memory” elements and “state machines”

2
Sequential Logic
Synchronous sequential circuits:
A system whose behavior can be defined form the
knowledge of its signals at discrete instants of time.

Asynchronous sequential circuits: a system whose

behavior depends on the order which its input signals
changes at any instance of time

3
4
5
Flip Flops

6
7
8
9
 NOR Gate SR Flip Flop :
The cross-coupled NOR gates creates an SR Flip Flop. Flip Flops are the basic
elements used in computer memory. The S input is called Set. The R input is called
Reset.

01
0 1
R 00
1 Q settles at S R Output
10
01 1
0 Q logic 0
Q changes 0 0 No Change Q stays at 0
Both
from outputs
1 to 0.
Q changes 0 1
settle to Reset: Q changes to 0
00.to
Called This
the
from 1.
01
0 breaks
reset the
mode!
Called the Set 1 0 Set: Q changes to 1
11
000
1 definition. This
00
1 Q mode! 1 1
condition is not Ambiguous : Not allowed!
S
allowed

Output Q and Q are by definition always opposite to each other. If Q=1 then Q =0.
Behaviour Table: Logic gates are defined by Truth Tables. Flip Flops are defined by behaviour
tables. Two different names for tables that do essentially the same job. To generate the behaviour
table you must assume an initial condition at output Q. This is necessary because the outputs are
wired to the inputs. This creates a feedback path that can only be analyzed when a starting point is
assumed.
Next S,R = 1,1 : The
Start
analysis
Next
with
S,R
S,R
procedure
= =1,0
0,1
0,0
: The
: The
works
analysis
analysis
as follows:
procedure
procedure
works
worksasasfollows:
follows:
1-Place the initial
1-Place
1-Place
conditions
the
theinitial
initial
at output
conditions
conditions
Q onat the
atoutput
output
diagram.
QQononAssume
the
thediagram.
diagram.
Q =0.Assume
AssumeQQ=0.
=1.
=0.
2-Place the input conditions at2-Place
2-Place
S and R.the
theinput
inputconditions
conditionsatatSSand
andR.R.
3-Analyze the top NOR gate 3-Analyze
and
3-Analyze
recordthe
the
Q. top
topNOR
NORgate
gateandandrecord
recordQ.
Q.
4-Analyze the bottom NOR4-Analyze
4-Analyze
gate and record
the
thebottom
bottom
Q. NOR
NORgate
gateandandrecord
recordQ.Q.
5-Repeat steps 3 and 4 until5-Repeat
5-Repeat
Q and Q steps
settle.
steps33and
and44until
untilQQand
andQQsettle.
settle.
Slide #14 14
 SR Flip Flop :
Cross-coupled NOR gates create an SR Flip Flop. It is easy to remember the operation
of an SR flip flop using only the symbol without repeatedly analyzing the cross
coupled NOR gate system.
The S input is called SET the R input is called reset.
They are both active high. Active high means that S =1 sets the flip
10
0 S Q 10
01 Output flop (S =0 does not set). R =1 resets the flip flop (R =0 does not reset).
Assume
Output
Q reset
does
reset
SETs
SETs
not
Q
starts
:change
:QQ=0.
=1.
at=0.
=1.
0. SET means set output Q to “1”.
00
1 R Q 01
10 RESET means reset output Q to “0”.

Symbol When S =0 and R =0 then Q does not change. Q holds its logic
level (1 or 0). It is equivalent to not issuing either the set or the
S=1
: :Hold
Hold
: R=1
Set
Mode
Mode
Mode
: : :: reset command.
reset Mode :
When S =1 and R =1 then Q is ambiguous. Both Q and Q outputs go to the same logic level which breaks the
definition of a flip flop. You can think of it this way … S =1 says SET and R =1 says reset. The flip flop does not
know whether the output should be Q =1 or Q =0. S=R=1 should never be used!
There is a second variety of SR flip flop that uses an active low S and R inputs. The internal system is cross coupled
NAND gates. Active low means that S =0 sets the flip flop (S =1 does not set). R =0 resets the flip flop (R =1 does not
reset).
When S =1 and R =1 then Q does not change. Q holds its logic
0 level (1 or 0). It is equivalent to not issuing either the set or the
1 S Q 1
0 Output
QAssume
doesSETs
not
Q reset command.
starts
change
: Q =1.
at 0.
1 When S =0 and R =0 then Q is ambiguous. The flip flop does not
0
1 R Q 0
1
know whether the output should be Q =1 or Q =0. S=R=0 should
never be used!
S=0 : SetMode
Mode
R=0
: HOLD
:reset Mode:::

Slide #15 15
 SR Flip Flop with a Positive Edge Triggered Clock Input :
A Positive EDGE triggered flip flop has a new input called clock. The clock requires a
transition from 0 to 1 in order that S and R controls output Q. Holding a constant logic 1
or a constant logic 0 at the clock input does not allow SR to change output Q.

An edge triggered clock is identified with “>Clk” on the symbol.

1 S Q 0
1 Output
Assume SETs
Q A transition from 0 to 1 at “>Clk” is required in order for the flip flop to
>Clk starts
: Q =1.
at 0. respond to S and R. This is called a” Positive Edge”.
0 R Q 1
0 Watch the animation to see how you would set the flip flop.

Holding “>Clk” at logic 1 will not result in S and R controlling Q. Only the 0
SR Flip Flop with edge
to 1 transition at “>Clk“ causes the output Q to change.
triggered clock
S=1 : Set Mode :
Inside the SR Flip Flop with Positive Edge Triggered Clock:

The clock signal is applied to the input.

1/0 S
2 1/0
0 S Q
>Clk 0 The NOT gate delays the signal because it has
1 a propagation delay. Propagation delay is the
R 3 1/0
0 R Q reaction time of the inverter. Let’s use 3 to 10
1/0
nanoSec.

3 to 10 nanoSec
delay.
During the 3 to 10 nanoSec interval, AND gate #1 outputs a 1. AND gates #2 and #3 transfer the logic levels to
internal SR and Q responds.
After the 3 to 10 nanoSec interval AND gate #1 outputs a 0. AND gates #2 and #3 transfer the logic 0 to
internal SR and Q holds(S=R=0 is Hold mode). To re-clock the flip flop you need another positive edge. Clock
Slide #16
must return to 0 and re-change back to 1.
16
 SR Flip Flop with a Negative Edge Triggered Clock Input :
A negative edge triggered flip flop requires a transition from 1 to 0 at at the clock input in
order for the flip flop to respond to S and R. This is called a” Negative Edge”. It is the
opposite of a positive edge triggered flip flop.

An edge triggered clock is identified with “o|>Clk” on the symbol.

1 S Q 0
1 Output
Assume SETs
Q Watch the animation to see how you would set the flip flop.
>Clk starts
: Q =1.
at 0.
Holding “o|>Clk” at logic 0 will not result in S and R controlling Q. Only the
0 R Q 1
0
1 to 0 transition at “o|>Clk“ causes the output Q to change.

SR Flip Flop with edge

triggered clock
S=1 : Set Mode :
Here is a summary of the flip flop devices

S Q S Q S Q S Q
>Clk >Clk
R Q R Q R Q R Q

Non-Clocked SR Edge Triggered

S and R control the response at Q only
S and R control the response when Clk is making a transition.
at Q continuously. On the edge of the clock signal.

Slide #17 17
 Note Pack 5 : Flip Flop Waveform Diagrams :
To draw waveforms for flip flops you need to begin with an initial condition at Q, mark the
area where the clock input is asserted and then draw the output response. Let’s use an
initial condition of Q =0.
The initial condition Q =0 is
marked as a dot on the output
waveform diagram.
Set
The flip flop has a negative edge
triggered clock. The clock is
Reset asserted when Clk makes a
transition from 1 to 0. The
asserted zone is marked off in
Clock yellow.

Analyze the waveform and draw

Q.
S Q
>Clk
R Q
Until
On
Onthe
this
thisclock
negative
negative
changes
edge
edgefrom
S=R=0:
S=11and
to No
0R=0:
it Change
is NOT
SET asserted.
Mode.
Mode.
Thus
ThusQQsetsholds
to at
1. Thus
0.
NoNoanalysis
Qanalysis
holds
is at
required
is 0.
requireduntil
until
thenext
next
negative edge.

Slide #18 18
Characteristic equations
Remember that the output
depends on the inputs and the
current state.

• First find the characteristic

table
Qt S R Qt+1
• Then derive the characteristic
equation for the RS flip flop. 0 0 0 0
SR 0 0 1 0
0 0 X 1 0 1 0 1
Qt 1 0 X 1 0 1 1 X
1 0 0 1
1 0 1 0
Qt+1=S+R’Qt 1 1 0 1
1 1 1 X
19
Gated D-Latch
Two inputs: D (data) and WE (write enable)
• when WE = 1, latch is set to value of D
S = NOT(D), R = D
• when WE = 0, latch holds previous value
S = R = 1

20
The D Flip Flop :
The D flip flop is used to store binary Data. The logic level at the “D” (data) input is
transferred to the Q output when the clock is asserted. It remains stored at output Q
until the clock is asserted a second time. That’s it … simple!

1
0 1
0
D Q
>Clk
Q

If look inside the D flip flop you can see how it works.

Let’s assume the initial conditions at Q are 0.

1
0 D 1
0 1
0 Set D to logic 1.
S Q
>Clk Show the logic levels at S and R
0
1
R Q The internal SR inputs are in the set mode. The flip flop will set
0
1 if D=1 and the clock is asserted. Q = D!

Set D to logic 0.
The internal SR inputs are in the reset mode. The flip flop will
reset if D=0 and the clock is asserted. Q = D again!

Slide #21
Characteristic equation for D flip flop

Qt D Qt+1 0 1
0 0 0
0 1 1 0 1
1 0 0
1 1 1 Q(t+1)=D
22
J K flip flop
It’s a refinement of RS flip flop , that defined the
indeterminate states in RS.
In RS flip flop the state 11 is not allowed ,
In JK flip flop the state 11 makes the flip flop changes
(switches) its output.

23
Mode of Operation: Hold

Hold: no change in Q.

J K Q Q’ Orig. Q Orig. Q’
0 0 0 1 0 1
Mode of Operation: Set

Set: Q = 1.

J K Q Q’ Orig. Q Orig. Q’
1 0 1 0 0 1
Mode of Operation: Reset

Reset: Q = 0.

J K Q Q’ Orig. Q Orig. Q’
0 1 0 1 1 0
Mode of Operation: Toggle

Toggle: Q = Q’.

J K Q Q’ Orig. Q Orig. Q’
1 1 1 0 0 1
Mode of Operation: Toggle again

Toggle: Q = Q’.

J K Q Q’ Orig. Q Orig. Q’
1 1 0 1 1 0
Overview: During a time period
Characteristic Equation

Q J K Q(t + 1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1 Characteristic Equation:
1 1 1 0 Q(t+1) = J.Q’+ K’.Q
Problem in JK flip flop:
•When J=1 ,K=1 and the clock is 1 , Qt+1=Q’t
•Assume Q=1, it will flip to 0 then to 1 then to 0 and so on
as long as the clock is 1.
•To avoid that the clock pulse (duration) must be less than
the propagation delay of the Flip flop.
•But this is not a solution.
•The solution is to build a Master slave or edge triggered
construction.

31
T flip flop
It’s a single input version of the JK Flip flop
T flip Flop has the same
Problem of JK when T=1

Qt T Qt+1 0 1
0 0 0
0 1 1 1 0
1 0 1
1 1 0 Qt+1=TQ’t+T’Qt
32
33
Master Slave D flip flop

34
Y= D; C=1 ‫عندما تكون‬
Y=Y when C=0

Q=Y when C=0

Q=Q when C=1

35
Master Slave RS flip flop

S S S Q

Master Slave

R R R Q’

CP

36
1

37
When CLK = 0 , gates 2,3 are not working,gate 2=1.
gate3=1  R=1,S=1
No change in the output.
If D=0; Gate 4=1, Gate1 =0.
If D=1; Gate 4=0, Gate1 =1.

38
IF D=0 Gate1=0,Gate4=1,Gate2=1,Gate3=1;
and CLK goes to 1
Gate 4=1, Gate 3=0, Gate1=0;Gate 2=1;
After the CLK being 1, if D changed to 1, this will not affect
on Gate 4 , nor any other gates.

39
IF D=1 Gate1=1,Gate4=0,Gate2=1,Gate3=1;
and CLK goes to 1
Gate 4=0, Gate 3=1, Gate1=1;Gate 2=0;
After the CLK being 1, if D changed to 0, Gate 4 =1 , other
gates will not affect by this change.

40
41
Positive edge triggered JK flip Flop from D flip flop

42
Positive Edge triggered T-Flip flop

43
Analysis of sequential circuit
The behavior of a seq. ckt is determined form
a) Inputs
b) Outputs
c) States of its flip flop

Both outputs and next state are function of input and

present state.
From a seq. ckt diagram , we will find the
a) state table
b) State diagram
c) State Equation

44
Example: analyze the following sequential circuit
CP

X
A B’
R Q’

A’ S Q
B
Y

B’ R Q’ A’
S Q
A
B
A

45
State Table

Present Next state Output

State
X=0 X=1 X=0 X=1

AB AB AB Y Y

00 00 01 0 0

01 11 01 0 0

10 10 00 0 1

11 10 11 0 0

46
Present Next state
State
xAB AB

000 00

001 11

010 10

011 10

100 01

101 01

110 00

111 11
47
State diagram
The state table can be represented graphically using the state diagram.
Transition from a state to state is shown as arrow labeled with two
values (Input/output) 0

00
1

1 01
10

11

48
State equation
State equation (or application equation) is an expression
that shows the relation for the next state of each flip flop
as a function of the present state and the inputs,
Method 1: using the characteristic equation of CPthe flip flop
QA(t+1) =S+R’QAt X
A
= X’.B+ (X.B’)’A R
B’

A’ S
= X’.B+(X’+B).A B
Y

= X’B+X’.A+A.B
B(t+1) = S+R’Q B’ R A’

= X.A’+(X’A)’.B B
S
A
A
= X.A’+X.B+A’.B

49
State equation
Method 2:
From the state table. AB
A(t+1) = 00 01 11 10

0 0 1 1 1
x
1 0 0 1 0

50
6.7 Design procedure
1. Build the state diagram
2. Build the state table
3. Assign binary values for each state
4. Determine the number of flip flops needed and assign a
symbol for each flip flop
5. Choose the type of flip flop to be used (we will use JK)
6. From the state table derive the excitation and output
tables
7. Simplify the flip flop functions
8. Draw the logic diagram

51
The following formulas for JK flip flop inputs will help us

Qt Qt+1
0 to 0 J=0, K=X ( don’t care)
0 to 1 J=1, K=X
1 to 0 J=X, K=1
1 to 1 J=X, K=0

52
Excitation tables for Flip Flops
Qt Qt+1 S R Qt Qt+1 J K
0 0 0 X 0 0 0 X
0 1 1 0 0 1 1 X
1 0 0 1 1 0 X 1
1 1 X 0 1 1 X 0
RS JK

Qt Qt+1 D Qt Qt+1 T

0 0 0 0 0 0

0 1 1 0 1 1

1 0 0 1 0 1

1 1 1 1 1 0
D T
53
Example 1
Design a circuit that works as a counter from 0 to 3 if the
input x is 1 and stay in the same state if x is 0
0

00
1 1
0
01 11
0
1 1
10

0 54
State table

X=0 X=1
AB AB AB
00 00 01
01 01 10
10 10 11
11 11 00

We have 4 states so we need 2 flip flops

55
Excitation table
Next state flip flop inputs
ABX AB JA KA JB KB
00 0 00 0 X 0 X
00 1 01 0 X 1 X
01 0 01 0 X X 0
01 1 10 1 X X 1
10 0 10 X 0 0 X
10 1 11 X 0 1 X
11 0 11 X 0 X 0
11 1 00 X 1 X 1

Now we need to simplify the equation of each flip flop

input
56
0 0 1 0 x x x X
x x x X 0 0 1 0

JA=Bx KA=Bx

0 1 x X x x 1 0
0 1 x x x x 1 0

JB=x KB=x

57
 QA
J

A
K

X QB
J

B
Clock K

58
Example 2
Design a counter that counts from 3 down to 0 one step
on each clock

59
Example 3
Design a circuit that works as a down counter from 3
down to 0 if the input x is 1 and stay in the same state if
x is 0

60
xAB AB Ta Tb
000 00 0 0
001 01 0 0
010 10 0 0
011 11 0 0
100 11 1 1
101 00 0 1
110 01 1 1
111 10 0 1

61
Example 4
Design a sequential circuit that counts from 0 to 3 if X=1
And from 3 down to 0 if X=0

Present Next Sa Ra Sb Rb
xAB AB
000 11 1 0 1 0
001 00 0 X 0 1
010 01 0 1 1 0
011 10 X 0 0 1
100 01 0 X 1 0
101 10 1 0 0 1
110 11 X 0 1 0
111 00 0 1 0 1

62
0 X 0 1
X 0 1 0

Ra=x’AB’+xAB

1 0 x 0

0 1 0 x

63
Example 5
Design a sequential Ckt that generates the following
sequence 000, 001, 010,100 , using T flip flops

This circuit has 4 states

00

01 11

10
64
 State Output

Inputs Combinational Ckt

Sequential Ckt

Clock

65
 Next Output
AB AB Ta Tb

00 01 0 1 000
01 10 1 1 001
10 11 0 1 010
11 00 1 1 100

66
Example 6
Repeat example 1 using RS flip flop
1) How RS Flip flop works
0 to 0 S=0, R=X ( don’t care)
0 to 1 S=1, R=0
1 to 0 S=0, R=1
1 to 1 S=X, R=0

2) Build the Excitation table, then simplify the equations

that represents R and S for each flip flop.

67
Excitation table
Next state flip flop inputs
ABX AB SA RA SB RB
00 0 00 0 X 0 X
00 1 01 0 X 1 0
01 0 01 0 X X 0
01 1 10 1 0 0 1
10 0 10 X 0 0 X
10 1 11 X 0 1 0
11 0 11 X 0 X 0
11 1 00 0 1 0 1

Now we need to simplify the equation of each flip flop

input
68
0 0 1 0 X X 0 X
X X 0 X 0 0 1 0

SA= RA=

0 1 0 X x 0 1 0
0 1 0 X x 0 1 0

SB= RB=

69
Example 7
Design an up_down counter that counts from 0 to 6,
depending on the input value, if x=0 it counts down, if 1 it
counts up
000
110
001
101

010
100

011

70
Present Next Da Db Dc
xABC ABC
0000 110 1 1 0
0001 000 0 0 0
0010 001 0 0 1
0011 010 0 1 0
0100 011 0 1 1
0101 100 1 0 0
0110 101 1 0 1
0111 XXX X X X
1000 001 0 0 1
1001 010 0 1 0
1010 011 0 1 1
1011 100 1 0 0
1100 101 1 0 1
1101 110 1 1 0
1110 000 0 0 0
71
1111 XXX X X X
1 0 0 0
0 1 X 1
1 1 x 0
0 0 1 0

Da=

72
details on example 7
We have a small problem here.
What if the counter started with 111 ?
We need to move it to one of the valid states,
To 000 for example
111
000
110
001
101

010
100

011 73
Non-Standard Counters

•Counters are sometimes defined that count in an

order other than standard numerical order.
•The state machine below is for a gray code counter
in which one bit changes at a time.

74
3 bit binary counter

75
76
77
Complete Example
A blinking traffic sign
• No lights on
• 1 & 2 on
• 1, 2, 3, & 4 on 3
4
• 1, 2, 3, 4, & 5 on 1
5
• (repeat as long as switch
2
is turned on)
• When the input is 0 , No lights on
DANGER
MOVE
RIGHT

78
 State Output

Inputs Combinational Ckt

Sequential Ckt

Clock

79
Traffic Sign State Diagram

Switch on
Switch off

State bit S1
State bit S0
Outputs

Transition on each clock cycle. 80

 Next state flip flop inputs
xAB AB Ta Tb
00 0 00
00 1 00
01 0 00
01 1 00
10 0 01
10 1 10
11 0 11
11 1 00
Now we need to simplify the equation of each flip flop
input

81
Traffic Sign Truth Tables
Outputs Next State: S1’S0’
(depend only on state: S1S0) (depend on state and input)
Lights 1 and 2 Switch

Lights 3 and 4 In S1 S0 S1’ S0’

Light 5
0 X X 0 0
S1 S0 Z Y X 1 0 0 0 1
0 0 0 0 0 1 0 1 1 0
0 1 1 0 0 1 1 0 1 1
1 0 1 1 0 1 1 1 0 0
1 1 1 1 1
Whenever In=0, next state is 00.

82
2 input Sequential Ckts
Q. Build a counter that counts from 0 to 3, this counter
has two inputs X,Y,
XY
00 Reset the counter ( go to state 00)
01 Count forward
10 Counts backward
11 No change

83
We have 4 states  we need two flip flops
We have 2 inputs  each state has 4 transitions

00

01 11

10
84
State table
Next state
Present state XY=00 XY=01 XY=10 XY=11
AB AB AB AB AB
00

01
10
11

85
Excitation table
XYAB AB TA TB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
86
1111
 Chapter 7

Registers, Counters, and Memory units

Gated D-Latch
Two inputs: D (data) and WE (write enable)
• when WE = 1, latch is set to value of D
S = NOT(D), R = D
• when WE = 0, latch holds previous value
S = R = 1

88
Register
A register stores a multi-bit value.
• We use a collection of D-latches, all controlled by a common WE.
• When WE=1, n-bit value D is written to register.

89
 4 bit register
A3 A2 A1 A0

Q Q Q Q

D D D D

Clock

I3 I2 I1 I0

90
Register with
parallel load

91
4 bit Shift right register

92
Serial
Transfer

93
94
Serial Adder

95
96
Ripple
counter

97
4 bit ribble couter (JK)
A0
A3 A2 A1

1 Q J 1 Q J 1 Q J 1
Q J
Clk Clk Clk Clk

K 1 K 1 K 1 K 1

98
Decimal counter

99
BCD Ripple
counter

100
•In BCD counter the first digit flips with the clock,
•The second digit flips depending on the first digit a clock
if the number is less than 8, since J is connected to Q8’
•When Q8 becomes 1, J will be 0, this will clear Q2.
•BUT this will take effect only after Q0 goes from 1 to 0.
•What about J8

101
MSI 4 bit counter with Parallel load

Load Clear

I0 A0
I1 A1
I2 A2
I3 A3

Clock

102
What is the different between if
Clear =1
Or
If load = 1 and the inputs are 0000

103
Using an MSI Binary counter , Build a BCD counter
•As you know, BCD counter goes to 0 after 9.
•All what we want to do is to load 0 if the counter value is 9

Load

I0 A0
I1 A1
I2 A2
I3 A3

0
Clock
104
www.datasheet4u.com

www.TI.com
105
Build a counter that counts from 0 to 6

106
Build a counter that counts from 5 to 13

107
Johnson counter
Self read.
Required for the exam.
0000
1000
1100
1110
1111
0111
0011
0001
0000

108
Memory Unit
•A memory unit stores binary information in groups called
words. Each is n bits.
•Memory size is the number of locations (words) that a
memory have.
•A memory word ( which contains binary numbers) is used
to represent an Instruction, Number, Character,…
•MAR
Read
•MDR
Write
M
A Memory
R

MDR
109
Binary Cell & RAM
Select

input Output
BC

Read/Write
R

S Q

110
111
112