AMSWeek 1

AMS/RF Custom Layout Training
• Analog Mixed Signal Layout
Design & Services Company for Analog, Digital and Embedded IPS SiliconBricks Confidential 1
Training Agenda for AMS/RF Layout Design
 CMOS IC Layout Design
 Schematic Fundamentals
 Overview of Semiconductor Fabrication Process
 Guidelines for Layout
CMOS IC Layout Design
 CMOS VLSI layout
 Layout in the Design Flow
Layout General Procedure
Quality Metrics For Layout Design
What Is CMOS VLSI Layout?
We define Layout Design as:

‘’The process of creating an accurate physical representation of an
engineering drawing (netlist) that confirms to constraints imposed by the
manufacturing process, the design flow and the performance
requirements shown to be feasible by simulation.”
Where Is Layout in the Design Flow?
• Market demand defines product
• Architects define the various sub-blocks
• System Designers define and verify the blocks
• Also validate that the idea can be
implemented (!)
• Circuit Designers perform digital and analog
simulation to verify circuit solution - gate
connectivity, sizes, etc. to meet specifications
•Layout Designers prepare the floorplan and
physical implementation
• Test the prototype
• Release to mass production
Types of Layout Design
Types of Layout Design
Layout General Procedure - LGP
LGP - Floorplan
LGP- Implement
LGP- Verification
LGP- Final Steps
Quality Metrics For Layout Design
Functionality Reuse ability
•Equivalence to Circuit Design •Equivalence to Circuit Design
•Multi Use
Cost
•IP Reuse
•Area
•Shrink - ability
•Porosity
Reliability
Performance
•Electromigration Rules
•Timing
•Margin to Manufacturing Rules
•Power
•ESD Protection
•Noise Immunity
•Latch Up Immunity
Manufacturability
ExecutionTiming
•Design Rule Checks
•Schedule
•Bonding Checks
•Number of Layout Changes
•Yield
•Effort Required for Change
Flow Compatibility •Maintain-ability
Functionality
Equivalence to Circuit Design
 Logical Equivalence
o Devices
 Transistors
 Resistors
 Capacitors
 Inductors
 Logical Equivalence
o Inputs
o Outputs
 Power Supplies
o Voltage Level
Verified by Layout Versus

Schematic check (LVS)
Cost - Area
 Smallest Area = Lowest Cost
 Fits in Budgeted Area
 Achieved By
o Early Floorplanning
o Proper Placement
o Minimum Routing
o Design Flow
o Packaging Options
 Flip Chip
 Wire Bond
 Q
– Second level
• Third level
– Fourth level
» Fifth level
Cost - Porosity
 Ratio of the total available routing
area to the total cell/device area
 Standard Cell Utilization depends on
Library Porosity
• For example M1 vs. M2 internal
layer density and direction
 Transistor/Device – Width of
Power lines do not have to be
compliant with Electromigration
(EM) rules at cell level
Performance – Timing - Delay
 Performance – Timing – Delay
 Minimize Wire RC Effects
• Performance – Timing - Margin
• Click to edit Master text

styles
– Second level
• Third level
– Fourth level
» Fifth level
Performance – Timing - Matching
Use Data Path Style Layout
Use Balanced and/or Symmetrical Layout
Performance – Power
To Minimize Power Reduce Parasitic
Capacitances
 Minimize Wire Length
 Minimize MOS Parasitics
Performance - Noise Immunity
 Design to Avoid Signal to Signal
Coupling Cross Talk
 Consider and Address Sources
of Substrate Noise
 Implement a Robust Power
Grid to Reduce Power Supply
Noise
Manufacturability - Design Rules
 Maximize Coverage of Design Rule Checks: Width, Spacing, etc
 Code Guidelines and “soft” rules
 Verified by Design Rule Check (DRC)
Manufacturability - Bonding
 Bonding Rules do not scale in sync with Process Technologies
Manufacturability - Yield
 Yield: % of Devices that are

Functional
• Manufacturing Process is
Not Perfect
• Using Greater than
Minimum (less than
Maximum) Design Rules
increases Yield
Flow Compatibility
 Layout Approaches Specific to Overall

Chip Design Flow
 ASIC
 Full Custom
 Memory
 Dependent on Region of the Chip

 I/O Ring
 Glue Logic
 Analog Block
 Interface Compatibility
 Reuse - Ability
Reuse - Ability - Interface Compatibility
 Interface = Boundary Characteristics
of Cell/Block
• Signal Connections
• Power Supply Connections
• Internal to External Layer Design
• Rules
 Cells/Block will be Instantiated in the
context of the overall design
• By Abutment
• Spaced
• Array
• Rotated
• Flip
• On Top
Reuse – Ability – Multi-Use
 Design for Multiple Versions on the same Die
 Metal Options to create Different Functionality
Reuse - Ability – IP reuse
Generalized Approach with

• Infrastructure for Reuse
• Full Documentation
• Usage Guidelines
• Scripts, Generators
• Version Control
• Design Related Models
• Verification Reports
 Layout Approaches
• Hierarchy
• Fully Verified Standalone
• Global Interface Compatibility
Reuse - Ability - Shrink - Ability
Drawn Layout is automatically
shrunk to produce smaller than
drawn results - Silicon Area Savings
when different process is used.
Should be Planned For
Use Specific Layout Approaches
 Special Design Rules
o Lambda Based
o Common Denominator
 Larger than Minimum Design Rules
CAD Techniques are also used
Reliability - Electromigration
Use Layout Techniques to
Minimize/Eliminate Failure
Mechanisms
 Wide Metals
Slits in Metals
45 Degree
Reliability - Margin Rules
Exceed Design Rules
Develop Project Layout Guidelines
Reliability - ESD Protection
 Special Layout Techniques Are Required
Reliability - Latch Up
 Use Liberal Substrate and Well Contacts
Execution - Schedule
Is Existing Flow Appropriate for the Current Undertaking?
Detailed Knowledge of the Tools and Flow
 Contingency
Execution - Effort for Change
Use Hierarchical Design Practices
 Understand and Automate Design Flow to ensure Repeatability
 Use Layout Design Techniques to Anticipate Change
Execution - Effort for Change
Version Control
 Freeze Completed Cells
 Avoid Unexpected Changes
Hierarchical Design
 Repeated Cells as Building Blocks
Decrease Single Block Complexity
 Parallel Activity
 Reduce Database Size
Schematic Fundamentals
 The MOS transistor: the basic circuit structure
 Logic gates
 Understanding the schematic connectivity
 Review of fundamental electrical laws
Schematic Fundamentals - Transistor
Basic transistors with bulk connection
 PMOS transistor turns “on” when a “0”

voltage is applied to gate - Source VDD,
VCC, AVD could be 1.0, 1.2, 1.8, 2.5, 3.3
Volts
NMOS transistor turns “on” when a “1”

voltage is applied to gate - Source is VSS,
AVS or any other “0” voltage
Schematic Fundamentals - Inverter
For layout the sizes of the NMOS and PMOS devices are
important
Inverter Views
Schematic Fundamentals - NAND
For (some) layout the ORDER of the series NMOS transistors
is important
NAND views
Schematic Fundamentals - NOR
For (some) layout the ORDER of the series PMOS transistors
is important
NOR views
Schematic Fundamentals - Complex
 Which implementation has fewer transistors?
Schematic Fundamentals - Complex
Schematic Fundamentals - Connectivity
Fundamental of Electric Laws
Introduction to Fabrication Process
Overview of Semiconductor Fabrication Process
The CMOS can be fabricated using different processes such as:
• N-well process for CMOS fabrication
• P-well process
• Twin tub-CMOS-fabrication process
The fabrication of CMOS can be done as shown below in twenty steps, by which
CMOS can be obtained by integrating both the NMOS and PMOS transistors on the
same chip substrate. For integrating these NMOS and PMOS devices on the same chip,
special regions called as wells or tubs are required in which semiconductor type and
substrate type are opposite to each other.
A P-well has to be created on a N-substrate or N-well has to be created on a P-
substrate. In this article, the fabrication of CMOS is described using the P-substrate, in
which the NMOS transistor is fabricated on a P-type substrate and the PMOS transistor
is fabricated in N-well.
The fabrication process involves twenty steps, which are as follows:

• Step1: Substrate
Primarily, start the process with a P-substrate.
• Step2: Oxidation
The oxidation process is done by using high-purity oxygen and hydrogen, which
are exposed in an oxidation furnace approximately at 1000 degree centigrade.
• Step3: Photoresist
A light-sensitive polymer that softens whenever exposed to light is
called as Photoresist layer. It is formed.
• Step4: Masking
The photoresist is exposed to UV rays through the N-well mask.
• Step5: Photoresist Removal

A part of the photoresist layer is removed by treating the wafer with
the basic or acidic solution.
• Step6: Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through the open area made by the
removal of photoresist using hydrofluoric acid.
• Step7: Removal of photoresist

The entire photoresist layer is stripped off, as shown in the below figure.
• Step8: Formation of the N-well

By using ion implantation or diffusion process N-well is formed.
• Step9: Removal of SiO2

Using the hydrofluoric acid, the remaining SiO2 is removed.
• Step10: Deposition of Polysilicon

Chemical Vapour Deposition (CVD) process is used to deposit a very thin
layer of gate oxide.
• Step11: Removing the layer barring a small area for the Gates
Except the two small regions required for forming the Gates of NMOS
and PMOS, the remaining layer is stripped off.
• Step12: Oxidation Process

Next, an oxidation layer is formed on this layer with two small regions for
the formation of the gate terminals of NMOS and PMOS.
• Step13: Masking and N-diffusion

By using the masking process small gaps are made for the purpose of N-
diffusion.
The n-type (n+) dopants are diffused or ion implanted, and the three n+
are formed for the formation of the terminals of NMOS.
• Step14: Oxide Stripping

The remaining oxidation layer is stripped off.
• Step15: P-Diffusion
Similar to the above N-diffusion process, the P-diffusion regions are
diffused to form the terminals of the PMOS.
• Step16: Thick Field Oxide

A thick-field oxide is formed in all regions except the terminals of the
PMOS and NMOS.
• Step17: Metallization
Aluminium is sputtered on the whole wafer.
• Step18: Removal of excess Metal

The excess metal is removed from the wafer layer.
• Step19: Terminals
The terminals of the PMOS and NMOS are made from respective gaps.
• Step20: Assigning the names of the terminals of the NMOS and PMOS
 Layout Dependent Effect (LDE)
 Concept of Device/Component Matching
 Signal Integrity Issues
 Failure Mechanism of Semiconductor Devices
 Physical Verification
Layout Dependent Effect (LDE)
• Well Proximity Effect (WPE)

• Length of OD Effect (LOD)
• Shallow Trench Isolation (STI)
• Poly Spacing Effect (PSE)
• OD/PO Density
Nano-scaled CMOS devices are so close to each other that they begin to interact.
Proximity effects can de-rate FET current by 10% (or more), or shift threshold by
several 10’s of mV. De-rating factors can only be calculated after layout extraction, i.e.
ignored in schematic-extracted net-lists. At 20nm, it’s not enough to model the
performance of a transistor or cell in isolation—where a device is placed in a layout,
and what is near to it, can change the behavior of the device. This is called layout-
dependent effect (LDE), and it has a big impact on performance and power. While LDE
was an emerging problem at 28nm, it is significantly worse at 20nm, where cells are
much closer together. At 20nm, up to 30% of device performance can be attributed to
the layout “context.” That is, the neighborhood in which a device is placed. A major
cause of LDE is mechanical stress, which is often intentionally induced to improve
CMOS transistor performance. For example, a dual stress liner is a silicon nitride (SiN)
capping layer that is intentionally deposited to be compressive on PMOS and tensile
on NMOS—improving the performance of both.
– Well Proximity Effect (WPE)-

• During the N+ ion implantation on STI induced process, some
implants reflect from the edges of the oxide and accumulates on
the part of active area forming non-uniform silicon surface.
• The WPE effect occurs to every MOS vicinity to the N-well

• changing electrical behavior of MOS regardless of: standard , high ,
low , thick/thin oxide devices.
• || ↑ if FET is too close to resist edge due to dopant ions scattering
off resist sidewall into active area during well implants.
• |Δ| depends on:
» FET channel distance to well mask edge
» Implanted ion species/energy.
• Other effects: µ ↓, ↑, ↑  ↓
• Well mask symmetry now critical for FET matching.
Graph Showing Vth vs Well Spacing
0.74
nwell
0.73
0.72 Wspc
0.71
Vth
0.7
0.69
Wspc
0.68
0.67
0 2 4 6 8
Wspc
– Length of OD Effect (LOD)
• An issue that’s closely related to STI is the length of diffusion

(LOD). The LOD is the distance from a n-channel or p-channel to
the STI oxide edge.
• As LOD grows shorter, more STI stress is placed on transistor gates.
From a standard cell's point of view, LOD is not necessarily context
dependent (dependent on proximity effects), because it usually
does not extend beyond the cell boundary, and its effect is already
accounted for when the cell is characterized.
• However, STI width is context dependent because it depends on
the distances of devices in neighboring cells.
• BSIM4 models for SPICE simulation provide two LOD parameters.

These are Sa, which specifies the distance to the left of the
channel, and Sb, which specifies the distance to the right of the
channel. Standard BSIM4 models do not, however, model STI
width, which is a more significant concern at 45 nm and below.
Sa Sb
– Shallow Trench Isolation (STI)

• The use of reverse bias p-n junctions to isolate transistors becomes
impractical as the transistor sizes decrease.
• Shallow trench isolation (STI) allows closer spacing of transistors by eliminating the depletion
region at the surface.
• If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniques such as
poly buffered LOCOS.
• At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads to
undesirable stress effects in the transistor.
• An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+ isolation
compared to LOCOS. This is a significant advantage for any process where there are implants
before STI.
Concept of Device/Component Matching
• Common Centroid Matching

• Inter-Leaving Matching
•Two devices with the same physical layout never have quite the same electrical properties.
•Variations between devices are called mismatches.
•Mismatches may have large impacts on certain circuit parameters, for example, the common mode rejection ratio
(CMRR).
•Mismatches may be either random or systematic, or a combination of both.
•Random mismatches are usually due to process variation.
•These process variations are usually manifestations of statistical variation, for example, in scattering of dopant
atoms or defect sites.
•Random mismatches cannot be eliminated, but they can be reduced by increasing device dimensions.
•In a rectangular device with active dimensions W by L, an area mismatch can be modeled as:
•Random mismatches thus scales as the inverse square root of the active device area.
Systematic mismatches may arise from imperfect balancing in a circuit.

• Simulations will readily show this source of systematic offset.
Usually, the circuit can be redesigned to minimize or even completely eliminate this type of systematic
offset.
Systematic mismatches may also arise from the gradients.
Certain physical parameters may vary gradually across an integrated circuit, for example:
Temperature
Pressure
Oxide Thickness
Even subtle gradients can produce large effects.
A 1C change in temperature produces a –2mV in , which equates to an 8% variation in .
–Common Centroid Matching
• The centroid of an array can be computed from the centroids of its segments.
• Arrays whose centroids coincide are called common-centroid arrays.
• Theoretically, a common-centroid array should entirely cancel systematic mismatches due to
gradients.
• Virtually all precisely matched components in integrated circuits use common centroids.
• A more elaborate sort of common-centroid array involves devices cross-coupled with a
rectangular two-dimensional array.
• This type of array is ideal for square devices, such as capacitors and MOS transistors.
• This type of array is called a cross-coupled pair.
• For many devices, particularly smaller ones, the cross-coupled pair provides the best possible layout.
• More complicated 2D arrays containing more segments provide better matching for large devices because they
minimize the impact of nonlinearities.
• The following rules summarize good design practices:
– Coincidence: The centroids of the matched devices should coincide, at least approximately. Ideally, the centroids
should exactly coincide.
– Symmetry: The array should be symmetric about both the X- and the Y-axes. Ideally, this symmetry should arise
from the placement of the segments in the array, and not from the symmetry of the individual segments.
– Dispersion: The array should exhibit the highest possible degree of dispersion; in other words, the segments of
each device should be distributed throughout the array as uniformly as possible.
– Compactness: The array should be as compact as possible. Ideally, it should be nearly square .
–Inter–Leaving Matching
• The simplest sort of common-centroid array consists of a series of devices arrayed in one
dimension.
• One-dimensional common-centroid arrays are ideal for long, thin devices, such as resistors.
• Since the segments of the matched devices are slipped between one another to form the array, the
process is often called inter-digitization.
Signal Integrity Issues
• Shielding
• Antenna Effect
• Electro-Migration
• IR Drop Analysis
The signal integrity issue hinders performance targets while the design integrity issue limits the reliability and
functionality targets. These effects have always existed, but become worse at deep sub-micron sizes because of
finer geometries, more metal layers, lower supply voltages, lower device threshold voltages.
The signal usually suffers from:
• Inherent noise: Noise resulting from the discrete and random movement of charge in a device, thermal noise,
flicker noise, and shot noise.
• Quantization noise: Noise resulting from the finite digital word size.
• Coupled noise (Crosstalk): Noise resulting from the signals adjacent circuits deeding into each other.
–Shielding
 One of the effective ways to reduce crosstalk noise.
 Shield is a wire connected directly to VDD or GND.
 One of the effective methods of shielding is placing ground or power lines at the sides of a victim signal line to reduce noise .
 The coupling capacitance between the two signal lines is replaced by two new coupling capacitance between the signal line and
shield line.
 Shield line isolates the voltage switching activities of the neighboring lines due to coupling capacitance.
–Antenna Effect
• Plasma Induced Damage (PID) also called Antenna Effect occurs during the manufacturing process.
• Antennae are floating conduction layers without shielding layer of oxide effects poly and metal layers.
• Charge accumulation on the metal layers could randomly discharge to the Gate terminal connected,
causing permanent damage to the gate-oxide breakdown.
• Antenna Ratio is defined as the total area and/or perimeter of conducting layer attached to the gate area
• During the etching of metal1 layer, the metal area acts as an “antenna”, collecting ions and then rising in
potential, therefore the gate voltage can increase so much that the gate oxide breaks down during
fabrication.
•To reduce the antenna effect:

– Routing options are used so that
» Break signal wires and route to upper metal layers by jumper insertion.
» All metal being etched is not connected to a gate until the last metal
layer is etched.
•Diode/Joggers insertion so that

– Connect reverse-biased diodes to the gate of the transistor.
– During normal circuit operation, the diode does not affect functionality.
– Connected of diodes only to those layers with antenna violations.
– One diode can be used to protect all input ports that are connected to the same output
ports.
•Electro-Migration
– Electro migration is the gradual displacement of metal atoms in a semiconductor.

– It occurs when the current density is high enough to cause the drift of metal ions in the
direction of the electron flow, and is characterized by the ion flux density.
•This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the
nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude
of forces that tend to dislodge them, including the current density, temperature and mechanical
stresses.
•The impact of EM is:
– Failure of the power supply lines to carry excessive current.

– Formation of open or short circuit, as current flows down narrow wires and metal atoms begins
to migrate and metal lines break over time due to metal fatigue.
•An example of failure mechanism of EM is shown below:

– A void where the outgoing ion flux exceeds the incoming ion flux, resulting in an open circuit.
– A hillock where the incoming ion flux exceeds the outgoing ion flux, resulting in a short
circuit.
Some layout techniques can aid to reduce EM by

•
Computation of current of the net/signal and provide adequate metallization.
Avoiding 90° corners and rapid wire width reduction.
Multiple (redundant) contacts and vias can help to reduce opens and improve
electro-migration stability.
IR Drop Analysis
IR-drop describes the DC voltage that develops across a conductor as a result of its
electrical resistance. This voltage is proportional to the current that flows though the
conductor (V=I.R) and results in a drop in voltage available at the load devices.
As silicon process geometries have reduced in scale over the years, so too have their
operating voltages and noise margins.
• A quick DC analysis of power and ground bus resistance can be used to catch gross
errors such as missing vias and undersized metallization.
• However, the power demands of many devices have not scaled accordingly and so
power-hungry devices, whilst operating at low voltage, can draw considerable
current. For a given power plane, a larger current will result in a greater IR-drop
voltage, and hence a lower voltage available at the load.
• The resistive power loss (I²R) is dissipated by the conductors in the form of heat,
and with significant resistances and/or very high currents, can be considerable.
• The voltage drop in supply lines from currents drawn by cells can cause chip
malfunctions on certain vectors and impacts speed and functionality of the
design.
• A poorly designed power mesh with inadequate metallization of power rails give
rise to localized ‘hot-spots’ with huge heat dissipation as shown in the image.
• Likewise, a good power budget in the design with proper interleaving/
slotting of power mesh to carry supply voltages to the transistors yield
reduction of IR drop.
Failure Mechanism of Semiconductor Devices
‒ LATCH-UP
– Causes of latch up
• Power Up
 Placing a device or board in a “hot socket” will create this situation.
 When subjected to hot-socket insertion, voltage conditions at the device pins are uncertain such
that the input diodes may be forward biased.
• Supply overvoltage
 Supply levels exceeding the absolute maximum rating can cause a CMOS circuit to latch up.
 Produce substrate current capable of triggering latch up.
 Latch-up is one of the reasons overvoltage should be avoided.
• Overshoot/Undershoot
 I/O pins experience the noisiest electrical environment.
 Fast switching signals can cause overshoot/undershoot
 Can cause forward biasing of diodes.
– Latch up in CMOS
• The source of Nmos,p substrate and Nwell forms the NPN parasitic transistor
• The drain of Pmos,N well and the P substrate forms the PNP parasitic transistor
– Latch up Prevention Technique in CMOS

• Use guard rings to remove the latch up problem
* N+ ring for PMOS and connect it to Vdd.
* P+ ring for NMOS and connect it to gnd.
• Use epitaxial layer
• Keep spacing between NMOS and PMOS
• Reducing Rsub and Rnwell
* Increasing the substrate and nwell doping density
* Using more number of source,substarte and nwell
contacts.
• Wider guard ring provide low resistive paths to minority carriers
– Latch up Prevention Technique in CMOS

• Guard rings form additional collectors for the parasitic transistors.
• Such collectors are connected either to the positive or negative supply-
voltage connection of the integrated circuit.
• The charge carriers injected into one of the two transistors is diverted
largely via these auxiliary collectors to the positive or negative supply-
voltage connection.
Physical Verification
– LVS
– DRC
– ERC
 Design Rule Check

• Objective: achieve a high overall yield and reliability
for the design.
 Layout Vs Schematic
 ERC (Electrical rule check)
• ERC (Electrical rule check) involves checking a design for all electrical
connections that are considered dangerous. This might include checking for
• Well and substrate areas for proper contacts and spacings thereby ensuring
correct power and ground connections
• Unconnected inputs or shorted outputs.
• Gates should not connect directly to supplies, it should be trough TIE
High/Low cells only.
• ERC checks are based upon assumptions about the normal operating
conditions of the ASIC, so they may give many false warning on ASICs with
multiple or negative supplies. They can also check for structures
susceptible to ESD damage.
EXTRA SLIDES
THEORY OF CMOS
 CMOS Technology Scaling & Challenges
• Channel Length Modulation

• Body Effect-Threshold Voltage
• Sub-Threshold Conduction
• Hot Carrier Effect
• Negative Bias Thermal Instability
• Drain Punch Through
• Short Channel Effect
CMOS Technology Scaling & Challenges
• One of the major change in a short-channel device is that the

electric field in the channel region becomes two-dimensional due to
the influence of the drain potential. Smaller transistors have various
undesired effects such as gate oxide degeneration due to ‘hot’
electrons, threshold voltage shift, gate-induced drain leakage, drain-
induced barrier lowering (DIBL). Changes in the fabrication flow have
to be introduced to mitigate these unwanted effects, and keep short-
channel devices operational.
– Channel Length Modulation-
In the Saturation region of operation of MOS devices, further
increase in will result in moving the pinch-off point towards the Source,
hence the effective length of the channel is reduced.
The physical channel length Lph = Ldrawn – 2LD

Lph is often called the effective channel length in the literature; here the term
‘physical channel length’ is chosen to avoid confusion with the effective
channel length introduced for the channel length modulation.
This Channel Length Modulation (λ) has a direct impact on

drain current as seen in the image below.
Body Effect-Threshold Voltage-

A MOSFET is a four terminal device; so far it is implicitly assumed that
the Source and the Bulk (Substrate/Body) are at zero potential.
The Source – Bulk junction always has to be reverse biased for the
normal operation of MOS to aid in inverse population of
electrons/holes to form a channel by creating a depletion region,
hence usually the bulk is connected to the most negative potential of
the circuit.
The Source - Body voltage, Influences the threshold voltage, hence the drain
current (sometimes the substrate is referred to as a second gate).
If > 0 (reverse bias), there will be an increase in charge since a

depletion region is created causing:
Increased Channel-substrate depletion
layer width.
Increased density of trapped carriers in
depletion layer
Increase in .
adds to the Channel-Substrate junction potential, Gate-Channel

• voltage drop increases, effectively.
When ≠ 0; the threshold voltage equation is defined as

Vthr= Vox + 2|φb | + Vf
Voxis the potential drop across the oxide (which charges up the depletion
region capacitance)
The term Vox without body-effect is
The term Vox with body-effect is
• φb is the “body potential”, and thus 2|φb | is the potential needed to

draw enough electrons
• Vfb is the “calibration” factor of the flat-band voltage.
• Sub-threshold Conduction
The transistor turns on suddenly when > and the transistor is completely off
when < (i.e. = 0).
In a real device a channel exists even for < (Although this channel resistance
is relatively high).
The region of operation that is defined by the initial creation of a channel and
the onset of strong inversion is called the weak inversion or sub-threshold
region.
The sub-threshold current increases exponentially with VGS hence in this region a
• MOST behaves like a BJT.
An important parameter for the sub-threshold operation of a MOS is the gate voltage
swing required to reduce the current from its ON value to an acceptable OFF value.
The sub-threshold gate voltage swing S is defined as the change in gate voltage to
reduce sub-threshold current by one decade.
Hot Carrier Effect
• As electrons move from the source to the drain in short device they can
acquire enough kinetic energy due to very high electric fields to cause impact
ionization.
• Such a hot carrier has enough kinetic energy to break lattice bonds and hence
create another electron–hole pair.
• Hot carriers have energies higher than kT, hence are not in thermal
equilibrium with the lattice.
The hot carrier electrons and the secondary electrons due to impact
• ionization are absorbed by the drain. Consequently, increases.
The holes are absorbed by the substrate and hence generate a substrate
current , which provides a good monitor as to the heating of the channel
carriers and to the electric field in the drain region.
• A large can cause a voltage drop in the substrate, as the substrate is usually
grounded this voltage drop can forward bias the source-to-substrate
junction.
Some hot carriers, although small in number, can acquire enough energy to
overcome the Si-SiO2 interface barrier (~ 3.2 eV for electrons, 4.9 eV for
holes) and thus get injected into the gate, resulting in a gate current, .
Some hot carriers also get trapped in the oxide, which changes the fixed
oxide charge and hence the threshold voltage and degrades the device
performance over time. This represents a long term reliability problem in
short channel devices.
Hot carrier injection tends to occur near the drain region since there the
electric field strength is higher.
Low doped drains (LDD) are the most popular drain structure for reducing
short channel effects.
• Negative Bias Thermal Instability-

NBTI is degrading of PMOS transistors.
Drain current gets decreased: transistor becomes weaker
Accelerated by raised T and VGS
NBTI can be modeled by pMOS shift:

• e.g. , nom = - 0.5V , deg = - 0.6V
Directly after end of stress,
shift is worse than long time
after end of stress.
Countermeasures against BTI-
induced drift
Symmetrical hold (no big impact)
Body biasing (Adapt bulk
oltage, expensie)
Burn-in (not so much degradation
anymore)
Limited operating temperature
(often not possible)
• Drain Punch Through

For larger , the depletion width is larger at the drain end since the drain
p-n junction is more reverse biased than the source p-n junction.
A wider depletion width obviously further decreases the charge
controlled by the gate voltage and hence lowers the threshold voltage
compared to = 0.
Consequently the drain depletion region moves closer to the source
depletion region which causes electric field penetration from drain to
source.
As a result, the potential barrier for electrons at the source is reduced;
hence more electrons are injected by the source over this reduced
potential barrier. This effect is called Drain Punch Through or Drain
Induced Barrier Lowering (DIBL).
The reduction in is linearly dependent on the :

() = – σ .
For short channel devices operating near the
threshold voltage, DIBL is a very important effect. In
saturation region, it mainly determines the output
resistance of the MOSFET.
 DIBL is influenced by a number of different process parameters (which are

basically the same as for the short channel length effect).
• The channel length: the shorter the channel, the higher the DIBL
• The gate oxide: the thicker the gate oxide, the higher the DIBL.
• The substrate doping: the higher the substrate doping, the lower the DIBL.
• The junction depth: The deeper the junction, the higher the DIBL.
• Substrate bias voltage: The higher the substrate bias the higher the DIBL.
• Short Channel Effect

The threshold voltage is independent of the channel length L and the channel
width W. This is only true for large geometry MOS (L, W > 10µm).
For smaller geometries the threshold voltage is a function of W, L:
For small channel lengths the threshold voltage decreases; for short channel
widths, the threshold voltage increases. [V].
• The reduction or increase in the threshold voltage becomes noticeable

when the channel length L (short channel transistor) or the channel width
W (narrow width transistor) becomes comparable with the source and
drain depletion widths or the depletion width under the channel,
respectively.
• The depletion regions of the source and drain overlap with the depletion
regions under the channel, especially at the source and drain ends of the
transistor.
Guidelines for Layout
 Layers and Connectivity
 Transistor Layout
Process Design Rules
 Vertical Connection Diagram
Guidelines for Power Lines
Guidelines for Transistors - Fingering
Layers and Connectivity
There are 4 basic layer types:
 Conductors - diffusion areas, polysilicon, metal, well layers
Isolation Layers - layers between the conductor layers
Contacts and vias - cuts in isolation layers
Implant layers - i.e. layers that define PMOS and NMOS devices
* There is a Difference between DRAWN and MASK layers
Transistor Layout
 Source/Drain
Gate
• LENGTH
• WIDTH
• Bulk connection
Nwell
Transistor Width Versus Length
Transistor Layout - Substrates
Wafer Cross Section Showing Bulk Connections

Transistor substrates versus well connections
Substrate - NMOS transistors
Nwell - PMOS transistors
Pwell or Rwell - NMOS transistors to new substrate voltage
Transistor Layout - Contacts
Vertical cut in the wafer to see how contacts and vias are
connecting between 2 conductors
Process Design Rules - Width Rule
 Active
Poly gate
Metal1
Metal2
Contact
90° and 45
Click to edit Master title style
 Active
Poly gate
 Metal1
Metal2
Contact
90° and 45 °
Minimum space or distance design rule

Process Design Rules - Space Rule
Example of space rule error between different layers and the

effect on the silicon transistor
Process Design Rules – Connectivity Based
Space Rule Connectivity Based – Nwell at different

potential
Process Design Rules - Overlap Rule
Possible Errors :
Shorts
 No transistor at all
Open Circuit
Inadequate
connection
Vertical Connection Diagram
• Click to edit Master text styles
– Second level
• Third level
– Fourth level
» Fifth level
Guidelines for Power Lines
Use results from power consumption simulation

 Use a consistent WIDTH over cells/blocks
Avoid power routed over cells - unless done by routers
Power grid simulation should consider - electromigration, IR
drop, RC delays
Power lines vias are adding resistance that has to be
included in simulations
Use a consistent WIDTH

over cells/blocks
Use results from

power consumption
Simulation
V1+V2 < m% of 3V
Guidelines for Signals
Minimize Input Delay
 Choose width based on
material characteristics and RC
simulation values
 Maintain preferred routing
directions
Standardize signals per layer
routing
Label signal names
Define # of vias per connection
Guidelines for Transistors - Templates
Cell templates
Examples
PMOS and NMOS regions
Power supply widths and position
Well regions and substrate connections
Boundary rules
Guidelines for Transistors - Fingering
 finger = minimum X
Dimension
 fingers = minimum
capacitance - best
 fingers = minimum Y
dimension
 All have the Identical
Transistor Width
Guidelines for Transistors - Soft Check
AMS/RF Custom Layout Training
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AMS/RF Custom Layout Training

• Analog Mixed Signal Layout

 CMOS IC Layout Design

 Overview of Semiconductor Fabrication Process

 Guidelines for Layout

 CMOS VLSI layout

 Layout in the Design Flow

Layout General Procedure

Quality Metrics For Layout Design

We define Layout Design as:

Verified by Layout Versus

• Click to edit Master text

 Code Guidelines and “soft” rules

 Verified by Design Rule Check (DRC)

 Bonding Rules do not scale in sync with Process Technologies

 Yield: % of Devices that are

 Layout Approaches Specific to Overall

 Dependent on Region of the Chip

Generalized Approach with

 CMOS IC Layout Design

 Overview of Semiconductor Fabrication Process

 Guidelines for Layout

 PMOS transistor turns “on” when a “0”

NMOS transistor turns “on” when a “1”

 Which implementation has fewer transistors?

 CMOS IC Layout Design

 Overview of Semiconductor Fabrication Process

 Guidelines for Layout

The fabrication process involves twenty steps, which are as follows:

• Step5: Photoresist Removal

• Step6: Removal of SiO2 using acid etching

• Step7: Removal of photoresist

• Step8: Formation of the N-well

• Step9: Removal of SiO2

• Step10: Deposition of Polysilicon

• Step12: Oxidation Process

• Step13: Masking and N-diffusion

• Step14: Oxide Stripping

• Step16: Thick Field Oxide

• Step18: Removal of excess Metal

 Layout Dependent Effect (LDE)

 Concept of Device/Component Matching

 Signal Integrity Issues

 Failure Mechanism of Semiconductor Devices

• Well Proximity Effect (WPE)

– Well Proximity Effect (WPE)-

• The WPE effect occurs to every MOS vicinity to the N-well

Graph Showing Vth vs Well Spacing

– Length of OD Effect (LOD)

• An issue that’s closely related to STI is the length of diffusion

• BSIM4 models for SPICE simulation provide two LOD parameters.

– Shallow Trench Isolation (STI)

• Common Centroid Matching

Systematic mismatches may arise from imperfect balancing in a circuit.

The signal usually suffers from:

 One of the effective ways to reduce crosstalk noise.

 Shield is a wire connected directly to VDD or GND.

•To reduce the antenna effect:

•Diode/Joggers insertion so that

– Electro migration is the gradual displacement of metal atoms in a semiconductor.

•The impact of EM is:

– Failure of the power supply lines to carry excessive current.

•An example of failure mechanism of EM is shown below: