IWPSD- 2013 GATE LEAKAGE CURRENT MODELLING IN A

FERROELECTRIC FET
Raheela Rasool, Najeeb-ud-din .
Department of Electronics & Communication Engineering
National Institute of Technology, Hazratbal
Srinagar 190 006, India
ABSTRACT
A gate leakage current model is proposed for a negative capacitance or ferroelectric FET (Fe-FET) based on Schottky and Poole-Frenkel emission.
It has been found that Poole-Frenkel current conduction mechanism takes place in ferroelectrics and the gate leakage currents in the gate stack
containing ferroelectric as dielectric can be modeled using a unified Schottky Poole-Frenkel model.

DEVICE STRUCTURE AND FRENKEL-POOLE IN FERROELECTRICS

-39.6
2.6 -38

0.5
-39.7

R(T) X 1E-4 (Cm/V)

-39.8 2.4 -39
-39.9 -40
Ln(J/E)

2.2

S(T)
-40.0
2.0 -41
-40.1
-40.2 1.8 -42
-40.3 1.6 -43
0.5 1.0 1.5 2.0 2.5 2.4 2.8 3.2 3.6 4.0
Electric Field X 1E7 (V/cm)
2.4 2.8 3.2 3.6 4.0
-1 -1
1000/T(K ) 1000/T (K )
Figure 2:.Analytical plot showing current density
Figure 3: Ferroelectric FET divided by electric field versus square root of electric Figure 3: Slope R(T) versus temperature (1/T) and Intercept
filed for bulk ferroelectric material S(T ) versus temperature (1/T)
GATE stack
UNIFIED SCHOTTKY POOLE-FRENKEL MODEL
The current due to P-F mechanism in the RNL is ASSUMPTIONS
modeled and is given as:
1. A key assumption is that the dielectric
constants considered for the two
equations are the same.
2. I-V characteristics of RNL in the
proposed model is independent of
bias voltage polarity.
The leakage current for the two reverse biased 3. Characteristics of the Schottky diode
Figure 4 : Model for current conduction if junctions is modeled and is given as D1 and D2 in the proposed model is
ferroelectric Gate stack not symmetrical but instead it has
highly conductive forward and less
conductive reverse I-V characteristics.

FORWARD BIAS REVERSE BIAS

6 2.8 6
6.9890
J*10 (A/cm )
2

5 2.7 6.9889 5
J*10 (A/cm )

(A/cm )
(A/cm )
2

2
1/2

4 2.6 6.9888 4
-21

6.9887
3 2.5 3
6.9886
-18

-18
-15

2
J*10

2.4 2
J*10

6.9885
1 2.3 6.9884 1
0.5 1.0 1.5 1/22.0 2.5 0.5 1.0 1.5 2.0 2.5 0.5 1.0 1.5 2.0 2.5 0.5 1.0 1.5 1/22.0 2.5
1/2
SQRT-V(V ) SQRT_V(V1/2) SQRT V(V ) SQRT-V(V )

Figure 5: Current density (J) plotted Figure 6: Current censity (J) plotted Figure 7: Fig.10 Current density(J) Figure 8: Current density(J)
against the square root of voltage for against the square root of voltage plotted against the square root of plotted against the square root of
resistor RNL for a schottky diode D2 voltage for a schottky diode D2 voltage for resistor RNL
CONCLUSIONS
The Current conduction mechanism in Ferroelectric dielectrics has been modeled as Poole-Frenkel mechanism. Also a unified Schottky-Poole-Frenkel model has been
proposed for the gate leakage currents in the gate stack of a ferroelectric FET. The model is proposed for a simple Fe-FET consisting of a ferroelectric material in the gate
stack, directly on the silicon substrate. However, this model has some practical implications, and can be improved, if we use a thin layer of some other dielectric better
compatible with silicon in between the ferroelectric and silicon substrate. Although there is a proof of concept of negative capacitance, still there is no practical device
available till now and therefore, scope for further research in this field
REFERENCES
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[2] G.F.Jiao et al,”Experimental studies of reliability issues in tunneling field effect transistors,”IEEE Electron Device Letters,vol.31,no.56,pp.396-398,may2010
[3] Chun Wing Yeung,Padilla,A.,Tsu-JaeKing Liu, Cheming Hu,”Programming characteristics of the steep turn-on/off feedback FET(FB-FET),”Symposium on VLSI Technology, vol.,no.,pp.176-
177,16-18 June 2009.
[4] S.Salahuddin and S.Datta,”Use of negative capacitance to provide voltage amplification for low power Nanoscale devices,”Nano Lett.,vol.8,no.2,pp.405-410,2008.
[5]S.M.Sze,”Physics of Semiconductor deices,”third edition, Wiley International