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anode cathode
P N
Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
p n
hole drift
electron drift
Charge
Density
+ x (b) Charge density.
Distance
-
Electrical
Field x
(c) Electric field.
V
Potential
(d) Electrostatic
x potential.
-W 1 W2
nMOS Transistor
Four terminals: gate (G), source (S), drain (D), body (B)
Gate–oxide–body stack looks like a capacitor
» Gate and body are conductors
» SiO2 (oxide) is a very good insulator
» Called metal – oxide – semiconductor (MOS) capacitor
» Even though gate is no longer made of metal
nMOS Operation (1/2)
Body is usually tied to ground (0 V)
When the gate is at a low voltage
» P-type body is at low voltage
» Source-body and drain-body diodes are OFF
» No current flows, transistor is OFF
nMOS Operation (2/2)
When the gate is at a high voltage
» Positive charge on gate of MOS capacitor
» Negative charge attracted to body
» Inverts a channel under gate to n-type
» Now current can flow through n-type silicon from source through channel to drain,
transistor is ON
pMOS Transistor
Similar, but doping and voltages reversed
» Body tied to high voltage (VDD)
» Gate “low”: transistor ON
» Gate “high”: transistor OFF
» Bubble indicates inverted behavior
Outline
The Fundamental MOSFETs
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
MOSFET as Switches
MOSFET: Metal-Oxide-Semiconductor Field-Effect
Transistor
0 Vx VDD (2.14)
x 0 means that Vx 0V
(2.15) (a) Power supply connection (b) Logic definitions
x 1 means that Vx VDD
Figure 2.11 Single voltage power supply
Switching Characteristics of MOSFET
In general,
Low voltages correspond to logic 0 values
High voltages correspond to logic 1 values
nFET
y x A which is valid iff A 1 (2.16)
pFET
y x A which is valid iff A 0 (2.17) (a) Open (b) Closed
» Use nFETs to pass logic 0 voltages of VSS = 0 V Figure 2.17 pFET pass characteristics
Outline
The Fundamental MOSFETs
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Basic Logic Gates in CMOS
Digital logic circuits are nonlinear networks that
use transistors as electronic switches to divert one
of the supply voltages VDD or 0 V to the output
(a) f = 1 output
(b) f = 0 output
Figure 2.18 General CMOS logic gate
Figure 2.19 Operation of a CMOS logic gate
The NOT Gate (1/2)
(a) x = 0 input
F (a, b, c) a (b c)
a (b c) (2.50)
[a (b c)] 1
F a 1 (b c) 1 (2.51)
Complex Logic Gate (2/3)
nFET array that
gives F=0 when
necessary
Figure 2.37 Logic function example Figure 2.39 nFET circuit for F
F a 1 (b c) 1
Figure 2.40 Karnaugh for nFET circuit
Figure 2.38 pFET circuit for F
function from equation (2.51)
Structured Logic Design (1/4)
CMOS logic gates are intrinsically inverting
» Output always produces a NOT operation acting on the input variables
(a) NAND - OR
(a) Parallel-connected pFETs
a b (a b) a b a b (2.73)
(a) Exclusive-OR (b) Exclusive-NOR
y x s iff s 1 (2.78)
A : Input
B : Output
C : Control Signal
0, Z (high impedance)
C
1, B A
Analysis of CMOS TG (2/4)
Case (A) Vin=Vdd, C=Vdd (Both transistors ON)
NMOS : PMOS :
Vds, n VDD Vout Vds, p Vout VDD
Vgs, n VDD Vout Vgs, p VDD
NMOS operation : PMOS operation :
1. Trun off , Vout VDD Vt , n 1. Saturation, Vout Vt , p
2. Saturation, Vout VDD Vt , n
2. Linear , Vout Vt , p
PMOS is always ON regardless of Vout Value
Region I Region II Region III
Total Current from I/P to O/P: ID = IDS,n+ISD,p
nMOS: saturation
pMOS: saturation
nMOS: saturation
pMOS: linear reg.
nMOS: cut-off
pMOS: linear reg.
Equivalent resistance of NMOS and PMOS
VDD Vout
reg , n VDDVout , reg , p
Vout Ids,n Isd , p
0V |Vt,p| (VDD-Vt,n) VDD
Summary of operating regions of MOS Equivalent R of TG = reg,n // reg,p
Analysis of CMOS TG (3/4)
Region (I): Vout < |Vt,p| { NMOS: saturation
PMOS: saturation
Region 1 Region 2 Region 3
2(VDD Vout)
reg , n nMOS: saturation nMOS: saturation nMOS: cut-off
n (VDD Vout Vt , n) 2 pMOS: saturation pMOS: linear reg. pMOS: linear reg.
2
reg , p ( simplify ) Vout
p [2(VDD Vt , p ) (VDD Vout)] 0V |Vt,p| (VDD-Vt,n) VDD
F P0 s P1 s (2.79)
» The 2-to-1 extended to a 4:1 network by using the 2-bit selector word (s1, so)
F P0 s1 s0 P1 s1 s0 P2 s1 s0 P3 s1 s0 (2.80)
Logic Design using TG (2/3)
TG based XOR/XNOR
ab ab a b a b a b a b a b
(2.81) (2.82)
TG based OR gate
f a (a) a b
a a b (2.83)
ab
Figure 2.64 An XNOR gate that used both TGs and FETs
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Clock and Dataflow Control
Synchronous digital design using a clock signal
» Simply, the switching characteristics of TGs
1
f (2.84)
T